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Электронный компонент: ICS8633-01

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ICS8634-01 Final Data Sheet
background image
8633AF-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
1
Integrated
Circuit
Systems, Inc.
ICS8633-01
1-
TO
-3 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8633-01 is a high performance 1-to-3
Differential-to-3.3V LVPECL Zero Delay Buffer
and a member of the HiPerClockSTM family of
High Performance Clock Solutions from ICS.
The ICS8633-01 has two selectable clock in-
puts. The CLKx, nCLKx pairs can accept most standard
differential input levels. Utilizing one of the outputs as feed-
back to the PLL, output frequencies up to 700MHz can be
regenerated with zero delay with respect to the input. Dual
reference clock inputs support redundant clock or multiple
reference applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Three differential 3.3V LVPECL outputs
Selectable differential clock inputs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for "zero delay" clock regeneration
Cycle-to-cycle jitter: 25ps (maximum)
Output skew: 25ps (maximum)
PLL reference zero delay: 50ps 100ps
3.3V operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
Available in both standard and lead-free RoHs-compliant
packages
HiPerClockSTM
ICS
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
SEL0
SEL1
MR
0
1
PLL
0
1
4, 8
Q0
nQ0
Q1
nQ1
Q2
nQ2
ICS8633-01
28-Lead, 209-MIL SSOP
5.3mm x 10.2mm x 1.75mm body package
F Package
Top View
PLL_SEL
V
CC
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
V
CC
nFB_IN
FB_IN
V
EE
V
CCA
V
EE
V
EE
V
CCO
V
CCO
Q2
nQ2
Q1
nQ1
Vcco
Vcco
Q0
nQ0
V
EE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
background image
8633AF-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
2
Integrated
Circuit
Systems, Inc.
ICS8633-01
1-
TO
-3 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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T
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T
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3B. PLL B
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background image
8633AF-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
3
Integrated
Circuit
Systems, Inc.
ICS8633-01
1-
TO
-3 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
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p
n
I
N
I
_
B
F
,
1
K
L
C
,
0
K
L
C
V
C
C
V
=
N
I
V
5
6
4
.
3
=
0
5
1
A
N
I
_
B
F
n
,
1
K
L
C
n
,
0
K
L
C
n
V
C
C
V
=
N
I
V
5
6
4
.
3
=
5
A
I
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C
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,
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6
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I
V
0
=
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,
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K
L
C
n
,
0
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C
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C
C
V
,
V
5
6
4
.
3
=
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V
0
=
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A
V
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T
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I
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E
t
n
e
r
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p
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r
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o
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1
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m
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t
n
e
r
r
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y
l
p
p
u
S
g
o
l
a
n
A
5
1
A
m
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
49C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
background image
8633AF-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
4
Integrated
Circuit
Systems, Inc.
ICS8633-01
1-
TO
-3 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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H
M
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
background image
8633AF-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
5
Integrated
Circuit
Systems, Inc.
ICS8633-01
1-
TO
-3 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
S
KEW
D
IFFERENTIAL
I
NPUT
L
EVEL
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
C
YCLE
-
TO
-C
YCLE
J
ITTER
-1.3V 0.165V
t
sk(o)
nQx
Qx
nQy
Qy
V
CMR
Cross Points
V
PP
V
CC
V
EE
CLK0,
CLK1
nCLK0,
nCLK1
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
P
ROPAGATION
D
ELAY
P
HASE
J
ITTER
& S
TATIC
P
HASE
O
FFSET
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q0:Q2
nQ0:nQ2
t
PD
CLK0,
CLK1
nCLK0,
nCLK1
Q0:Q2
nQ0:nQ2
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
Q0:Q2
nQ0:nQ2
(where
t
() is any random sample, and
t
()
mean
is the average
of the sampled cycles measured on controlled edges)
t
()
mean
= Static Phase Offset
t
()
V
OH
V
OL
V
OH
V
OL
nCLK0,
nCLK1
nFB_IN
FB_IN
t
jit() =
t
() --
t
()
mean
= Phase Jitter
CLK0,
CLK1
V
CC
,
V
CCA
,
V
CCO
V
EE

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