8634BY-01
www.icst.com/products/hiperclocks.html
REV. B MARCH 5, 2003
1
Integrated
Circuit
Systems, Inc.
ICS8634-01
1-
TO
-5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8634-01 is a high performance 1-to-5 Dif-
ferential-to-3.3V LVPECL Zero Delay Buffer and a
member of the HiPerClockSTM family of High Perfor-
mance Clock Solutions from ICS. The ICS8634-01
has two selectable clock inputs. The CLKx, nCLKx
pair can accept most standard differential input levels. Utilizing
one of the outputs as feedback to the PLL, output frequencies up
to 700MHz can be regenerated with zero delay with respect to
the input. Dual reference clock inputs support redundant clock
or multiple reference applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
5 differential 3.3V LVPECL outputs
Selectable differential clock inputs
CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for "zero delay" clock regeneration
Cycle-to-cycle jitter: 25ps (maximum)
Output skew: 25ps (maximum)
PLL reference zero delay: 50ps 100ps
3.3V operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
CCO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
CCO
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
V
CCO
Q0
nQ0
V
EE
V
EE
FB_IN
nFB_IN
V
CC
V
CCO
nQ4
Q4
V
EE
V
EE
V
CCA
PLL_SEL
V
CC
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8634-01
HiPerClockSTM
,&6
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
SEL0
SEL1
MR
0
1
PLL
0
1
4, 8
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
8634BY-01
www.icst.com/products/hiperclocks.html
REV. B MARCH 5, 2003
3
Integrated
Circuit
Systems, Inc.
ICS8634-01
1-
TO
-5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
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3
=
0
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S
_
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=
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3
=
5
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r
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,
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_
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L
C
V
C
C
V
,
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5
6
4
.
3
=
N
I
V
0
=
5
-
A
L
E
S
_
L
L
P
V
C
C
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
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B
F
,
1
K
L
C
,
0
K
L
C
V
C
C
V
=
N
I
V
5
6
4
.
3
=
0
5
1
A
N
I
_
B
F
n
,
1
K
L
C
n
,
0
K
L
C
n
V
C
C
V
=
N
I
V
5
6
4
.
3
=
5
A
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r
r
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C
w
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N
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F
,
1
K
L
C
,
0
K
L
C
V
C
C
V
,
V
5
6
4
.
3
=
N
I
V
0
=
5
-
A
N
I
_
B
F
n
,
1
K
L
C
n
,
0
K
L
C
n
V
C
C
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
V
P
P
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t
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1
.
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.
1
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2
,
1
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m
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5
.
0
+
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C
C
5
8
.
0
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s
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1
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,
1
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w
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m
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5
1
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m
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, V
O
-0.5V to V
CCO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8634BY-01
www.icst.com/products/hiperclocks.html
REV. B MARCH 5, 2003
5
Integrated
Circuit
Systems, Inc.
ICS8634-01
1-
TO
-5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
S
KEW
D
IFFERENTIAL
I
NPUT
L
EVEL
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
V
CC
, V
CCA
, V
CCO
= 2V
C
YCLE
-
TO
-C
YCLE
J
ITTER
V
EE
= -1.3V 0.165V
tsk(o)
nQx
Qx
nQy
Qy
V
CMR
Cross Points
V
PP
V
CC
V
EE
CLK0,
CLK1
nCLK0,
nCLK1
O
UTPUT
R
ISE
/F
ALL
T
IME
odc & t
P
ERIOD
P
ROPAGATION
D
ELAY
P
HASE
J
ITTER
& S
TATIC
P
HASE
O
FFSET
Clock Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q0:Q4
nQ0:nQ4
t
PD
CLK0,
CLK1
nCLK0,
nCLK1
Q0:Q4
nQ0:nQ4
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
Q0:Q4
nQ0:nQ4
(where
t () is any random sample, and t()
mean
is the average
of the sampled cycles measured on controlled edges)
t()
mean
= Static Phase Offset
t()
V
OH
V
OL
V
OH
V
OL
nCLK0,
nCLK1
nFB_IN
FB_IN
tjit() = t() -- t()
mean
= Phase Jitter
CLK0,
CLK1
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