8701I
www.icst.com/products/hiperclocks.html
REV. A MARCH 16, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
1,
2
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS8701I is a low skew, 1, 2 Clock Gen-
erator and a member of the HiPerClockSTM
family of High Performance Clock Solutions
from ICS. The low impedance LVCMOS out-
puts are designed to drive 50
W
series or par-
allel terminated transmission lines. The effective fanout can
be increased from 20 to 40 by utilizing the ability of the
outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the 1,
2 or a combination of 1 and 2 modes. The bank enable
inputs, BANK_EN0:1, support enabling and disabling each
bank of outputs individually. The master reset input, nMR/
OE, resets the internal frequency dividers and also con-
trols the active and high impedance states of all outputs.
The ICS8701I is characterized at 3.3V and mixed 3.3V in-
put supply, and 2.5V output supply operating modes. Guar-
anteed bank, output and part-to-part skew characteristics
make the ICS8701I ideal for those clock distribution appli-
cations demanding well defined performance and repeat-
ability.
F
EATURES
20 LVCMOS outputs, 7
W
typical output impedance
Output frequency up to 250MHz
200ps bank skew, 250ps output skew, 300ps multiple
frequency skew, 600ps part-to-part skew
LVCMOS / LVTTL clock input
LVCMOS control inputs
Bank enable logic allows unused banks to be disabled
in reduced fanout applications
3.3V or mixed 3.3V input, 2.5V output operating
supply modes
48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
-40C to 85C ambient operating temperature
Other divide values available on request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
QAO - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
LVCMOS_CLK
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23
24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
QC3
VDDO
QC4
QD0
VDDO
QD1
GND
QD2
GND
QD3
VDDO
QD4
QB1
VDDO
QB0
QA4
VDDO
QA3
GND
QA2
GND
QA1
VDDO
QA0
DIV_SELA
DIV_SELB
L
VCMOS_CLK
GND
VDDI
BANK_EN0
GND
BANK_EN1
VDDI
nMR/OE
DIV_SELC
DIV_SELD
GND
QB2
GND
QB3
VDDO
QB4
QC0
VDDO
QC1
GND
QC2
GND
48-Pin LQFP
Y Package
Top View
ICS8701I
HiPerClockSTM
,&6
1
0
1
2
1
0
1
0
1
0
Bank Enable
Logic
8701I
www.icst.com/products/hiperclocks.html
REV. A MARCH 16, 2001
4
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
1,
2
C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage
4.6V
Inputs
-0.5V to VDD + 0.5V
Outputs
-0.5V to VDDO + 0.5V
Ambient Operating Temperature
-40C to 85C
Storage Temperature
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of product at these condition or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
VDDI=VDDO=3.3V5%, T
A
=-40C
TO
85C
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A
m
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
VDDI=VDDO=3.3V5%, T
A
=-40C
TO
85C
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