Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- PLL Enable Function Table
- PLL Bypass Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- LVCMOS 3.3V DC Characteristics
- Differential 3.3V DC Characteristics
- 3.3V AC Characteristics
- Power Supply 2.5V DC Characteristics
- LVCMOS 2.5V DC Characteristics
- Differential 2.5V DC Characteristics
- 2.5V AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- 2.5V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Output Skew Diagram
- Cycle-to-Cycle Jitter Diagram
- Output Rise/Fall Time Diagram
- Phase Jitter & Static Phase Offset Diagram
- Propagation Delay
- tPW, odc & tPeriod Diagram
- Application Information
- Power Supply Filtering Techniques
- Wiring the Differential Input to Accept Single Ended Levels
- Single Ended Signal Driving Differential Input Diagram
- Differential Clock Input Interface
- HiPerClockS CLK/nCLK Input Driven by ICS HiPerClockS LVHSTL Driver Diagram
- HiPerClockS CLK/nCLK Input Driven by LVPECL Driver Diagrams
- HiPerClockS CLK/nCLK Input Driven by LVDS Driver Diagram
- Layout Guideline
- LVCMOS Clock Generator Schematic Example
- Power & Grounding
- Clock Traces & Termiantion
- PCB Board Layout
- Reliability Information
- Tansistor Count
- Package Outline
- Package Dimensions
- Ordering Information
8705BY
www.icst.com/products/hiperclocks.html
REV. G JUNE 16, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS8705 is a highly versatile 1:8 Differen-
tial-to-LVCMOS/LVTTL Clock Generator and a
member of the HiPerClockSTM family of High Per-
formance Clock Solutions from ICS. The ICS8705
has two selectable clock inputs. The CLK1,
nCLK1 pair can accept most standard differential input lev-
els. The single ended CLK0 input accepts LVCMOS or LVTTL
input levels.The ICS8705 has a fully integrated PLL and can
be configured as zero delay buffer, multiplier or divider and
has an input and output frequency range of 15.625MHz to
250MHz. The reference divider, feedback divider and output
divider are each programmable, thereby allowing for the fol-
lowing output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2,
1:4, 1:8. The external feedback allows the device to achieve
"zero delay" between the input clock and the output clocks.
The PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference clock
is routed around the PLL and into the internal output dividers.
F
EATURES
8 LVCMOS/LVTTL outputs, 7
typical output impedance
Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs
CLK1, nCLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
CLK0 input accepts LVCMOS or LVTTL input levels
Output frequency range: 15.625MHz to 250MHz
Input frequency range: 15.625MHz to 250MHz
VCO range: 250MHz to 500MHz
External feedback for "zero delay" clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Fully integrated PLL
Cycle-to-cycle jitter: 45ps (maximum)
Output skew: CLK0, 65ps (maximum)
CLK1, nCLK1, 55ps (maximum)
Static Phase Offset: 25 125ps (maximum), CLK0
Full 3.3V or 2.5V operating supply
Lead-Free package available
Industrial temperature information available upon request
HiPerClockSTM
ICS
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32-Lead LQFP
7mm x 7mm x 1.4 mm
Y Package
Top View
V
DDO
Q5
GND
Q4
V
DDO
Q3
GND
Q2
SEL0
SEL1
CLK0
nc
CLK1
nCLK1
CLK_SEL
MR
V
DDO
Q1
GND
Q0
V
DDO
SEL2
FB_IN
V
DD
Q6
GND
Q7
V
DDO
SEL3
V
DDA
PLL_SEL
V
DD
ICS8705
PLL_SEL
CLK0
CLK1
nCLK1
CLK_SEL
FB_IN
SEL0
SEL1
SEL2
SEL3
MR
0
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
2, 4, 8, 16,
32
,
64, 128
0
1
8705BY
www.icst.com/products/hiperclocks.html
REV. G JUNE 16, 2004
2
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
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8705BY
www.icst.com/products/hiperclocks.html
REV. G JUNE 16, 2004
3
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
T
ABLE
3A. PLL E
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8705BY
www.icst.com/products/hiperclocks.html
REV. G JUNE 16, 2004
4
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, TA = 0C
TO
70C
l
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m
y
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3
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3
5
6
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0
2
A
m
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, TA = 0C
TO
70C
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V
D
D
V
,
V
5
6
4
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3
=
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=
5
-
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S
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L
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V
,
V
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3
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3
.
3
"
e
e
s
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8705BY
www.icst.com/products/hiperclocks.html
REV. G JUNE 16, 2004
5
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, TA = 0C
TO
70C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, TA = 0C
TO
70C
l
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4
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O
N
8705BY
www.icst.com/products/hiperclocks.html
REV. G JUNE 16, 2004
6
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V5%, TA = 0C
TO
70C
T
ABLE
4F. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V5%, TA = 0C
TO
70C
T
ABLE
4E. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V5%, TA = 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
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P
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8705BY
www.icst.com/products/hiperclocks.html
REV. G JUNE 16, 2004
7
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
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6
d
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T
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N
8705BY
www.icst.com/products/hiperclocks.html
REV. G JUNE 16, 2004
8
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
D
IFFERENTIAL
I
NPUT
L
EVEL
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V5%
-1.165V5%
O
UTPUT
S
KEW
C
YCLE
-
TO
-C
YCLE
J
ITTER
O
UTPUT
R
ISE
/F
ALL
T
IME
SCOPE
Qx
LVCMOS
1.25V5%
-1.25V5%
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
V
DD
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
Q0:Q7
V
DDO
2
V
DDO
2
V
DDO
2
t
cycle n
t
cycle n+1
tsk(o)
V
DDO
2
V
DDO
2
Qy
Qx
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
GND
GND
V
DD
,
V
DDA
,
V
DDO
V
DD
,
V
DDA
,
V
DDO
8705BY
www.icst.com/products/hiperclocks.html
REV. G JUNE 16, 2004
9
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
P
ROPAGATION
D
ELAY
P
HASE
J
ITTER
& S
TATIC
P
HASE
O
FFSET
Q0:Q7
t
PD
V
DDO
2
V
DD
2
CLK1
nCLK1
CLK0
t
PW
t
PERIOD
V
DDO
2
V
DDO
2
V
DDO
2
t
PW
t
PERIOD
odc =
Q0:Q7
(where
t() is any random sample, and t()
mean
is the average
of the sampled cycles measured on controlled edges)
t()
mean
= Static Phase Offset
t
()
V
OH
V
OL
V
OH
V
OL
V
DDO
2
nCLK1
FB_IN
t
jit() =
t
() --
t
()
mean
= Phase Jitter
CLK1
8705BY
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REV. G JUNE 16, 2004
10
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
A
PPLICATION
I
NFORMATION
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8705 provides sepa-
r a t e p o w e r s u p p l i e s t o i s o l a t e a n y h i g h s w i t c h i n g
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
8705BY
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REV. G JUNE 16, 2004
11
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
F
IGURE
3C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 3A to 3D show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
3A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 4A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
8705BY
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REV. G JUNE 16, 2004
12
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
C4
0.1uF
VDD
VDD
R4
1K
Zo = 50
VDD
R7
10 - 15
VDD
R2
43
RD1
Not Install
(U1-24)
(U1-32)
Logic Input Pin Examples
C3
0.1uF
R5
1K
SEL2
C7
0.1uF
To Logic
Input
pins
(U1-9)
VDD
U1
ICS8705
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
SEL0
SEL1
CLK0
nc
CLK1
nCLK1
CLK_SEL
MR
VD
D
FB
_
I
N
SEL
2
V
DDO
Q0
GN
D
Q1
V
DDO
Q2
GND
Q3
VDDO
Q4
GND
Q5
VDDO
VD
D
PLL_
SEL
VD
D
A
SEL
3
VD
D
O
Q7
GN
D
Q6
VDD=3.3V or 2.5V
To Logic
Input
pins
R4
43
VDD
C16
10u
PLL_
SEL
R1
43
C2
0.1uF
Zo = 50
Zo = 50
(U1-12)
(U1-16)
(U1-28)
SEL3
SEL1
RU2
Not Install
VDDA
C1
0.1uF
Ro ~ 7 Ohm
Driv er_LVCMOS
(U1-20)
SEL0
C5
0.1uF
Set Logic
Input to
'1'
RU1
1K
Set Logic
Input to
'0'
C6
0.1uF
RD2
1K
C11
0.01u
L
AYOUT
G
UIDELINE
The schematic of the ICS8705 layout example is shown in
Figure 4A. The ICS8705 recommended PCB board layout
for this example is shown in
Figure 4B. This layout example is
used as a general guideline. The layout in the actual system will
depend on the selected component types, the density of the
components, the density of the traces, and the stack up of the
P.C. board.
F
IGURE
4A. ICS8705 LVCMOS C
LOCK
G
ENERATOR
S
CHEMATIC
E
XAMPLE
8705BY
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REV. G JUNE 16, 2004
13
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
Other
signals
GND
VDDA
R7
C7
50 Ohm
Trace
C11
VIA
C16
Pin 1
R2
U1
C5
50 Ohm
Trace
VDD
R1
C2
C4
C6
C1
C3
F
IGURE
4B. PCB B
OARD
L
AYOUT
F
OR
ICS8705
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred. This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
DDA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have same
length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The series termination resistors should be located as
close to the driver pins as possible.
8705BY
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REV. G JUNE 16, 2004
14
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8705 is: 3126
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8705BY
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REV. G JUNE 16, 2004
15
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
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8705BY
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REV. G JUNE 16, 2004
16
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
8705BY
www.icst.com/products/hiperclocks.html
REV. G JUNE 16, 2004
17
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
T
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