Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Descriptions continued
- Pin Characteristics
- Output Control Pin Function Table
- Operating Mode Function Table
- PLL Input Function Table
- Control Function Tables
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- LVCMOS 3.3V DC Characteristics
- 3.3V AC Characteristics
- Power Supply 3.3V/2.5V DC Characteristics
- LVCMOS 3.3V/2.5V DC Characteristics
- 3.3V/2.5V AC Characteristics
- Crystal Characteristics
- PLL Input Reference Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- 3.3V/2.5V Output Load AC Test Circuit Diagram
- Output Skew Diagram
- Bank Skew Diagram
- Cycle-to-Cycle Jitter Diagram
- Static Phase Offset Diagram
- tPW & tPeriod Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Power Supply Filtering Techniques
- Power Supply Filtering Diagram
- Crystal Input Interface
- Schematic Example
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
OEA
MR
D_SELA0
D_SELA1
REF_CLK
XTAL_SEL
FB_IN
PLL_SEL
OEB
D_SELB1
D_SELB0
OEC
D_SELC1
D_SELC0
OED
D_SELD1
D_SELD0
FBDIV_SEL1
FBDIV_SEL0
G
ENERAL
D
ESCRIPTION
The ICS8761 is a low voltage, low skew PCI /
PCI-X Clock Generator and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS8761 has a selectable
REF_CLK or crystal input. The REF_CLK input
accepts LVCMOS or LVTTL input levels. The ICS8761 has a
fully integrated PLL along with frequency configurable clock
and feedback outputs for multiplying and regenerating clocks
with "zero delay". Using a 20MHz or 25MHz crystal or a
33.333MHz or 66.666MHz reference frequency, the ICS8761
will generate output frequencies of 33.333MHz, 66.666MHz,
100MHz and 133.333MHz simultaneously.
The low impedance LVCMOS/LVTTL outputs of the ICS8761
are designed to drive 50
series or parallel terminated
transmission lines.
F
EATURES
Fully integrated PLL
17 LVCMOS/LVTTL outputs, 15 typical output impedance
Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_CLK
Maximum output frequency: 166.67MHz
Maximum crystal input frequency: 38MHz
Maximum REF_CLK input frequency: 83.33MHz
Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz simultaneously
Separate feedback control for generating PCI / PCI-X
frequencies from a 20MHz or 25MHz crystal or 33.333MHz
or 66.666MHz reference frequency
Cycle-to-cycle jitter: 70ps (maximum)
Period jitter, RMS: 17ps (maximum)
Output skew: 230ps (maximum)
Bank skew: 40ps (maximum)
Static phase offset: 0 150ps (maximum)
Full 3.3V or 3.3V core, 2.5V multiple output supply modes
0C to 85C ambient operating temperature
Lead-Free package available
HiPerClockSTM
ICS
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
XTAL1
XTAL2
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
FB_OUT
3
4
6
12
0 0
0 1
1 0
1 1
0
1
0 0
0 1
1 0
1 1
QC0
QC1
QC2
QC3
QD0
QD1
QD2
QD3
PLL
OSC
0
1
6
12
16
20
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
64-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
ICS8761
REF_CLK
GND
XTAL1
XTAL2
V
DD
XTAL_SEL
PLL_SEL
V
DDA
V
DD
D_SELC0
D_SELC1
OEC
OEA
D_SELA0
D_SELA1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND
FB_OUT
V
DDOFB
FB_IN
V
DD
FBDIV_SEL0
FBDIV_SEL1
MR
V
DD
D_SELD0
D_SELD1
OED
OEB
D_SELB0
D_SELB1
GND
GND
QA0
V
DDOA
QA1
GND
QA2
V
DDOA
QA3
GND
QB0
V
DDOB
QB1
GND
QB2
V
DDOB
QB3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND
QC0
V
DDOC
QC1
GND
QC2
V
DDOC
QC3
GND
QD0
V
DDOD
QD1
GND
QD2
V
DDOD
QD3
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
2
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
T
ABLE
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8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
3
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
T
ABLE
2. P
IN
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8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
4
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
T
ABLE
3D. C
ONTROL
F
UNCTION
T
ABLE
T
ABLE
3E. C
ONTROL
F
UNCTION
T
ABLE
(PCI C
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8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
5
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDOX
= 3.3V5%, T
A
= 0C
TO
85C
l
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p
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"
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDOx
+ 0.5V
Package Thermal Impedance,
JA
41.1C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
6
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDOX
= 3.3V5%, T
A
= 0C
TO
85C
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8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
7
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
T
ABLE
4C. P
OWER
S
UPPLY
DC C
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,
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DD
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X
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A
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TO
85C
T
ABLE
4D. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
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= 3.3V5%, V
DDO
X
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A
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"
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
8
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
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6. C
RYSTAL
C
HARACTERISTICS
T
ABLE
7. PLL I
NPUT
R
EFERENCE
C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
X
= 3.3V5%, T
A
= 0C
TO
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DD
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T
O
N
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
9
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
B
ANK
S
KEW
(Where X denotes outputs in the same Bank)
O
UTPUT
S
KEW
t
PW
& t
P
ERIOD
C
YCLE
-
TO
-C
YCLE
J
ITTER
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
S
TATIC
P
HASE
O
FFSET
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
LVCMOS
2.05V5%
V
DDOx
-1.25V5%
V
DD
,
V
DDA
1.25V5%
SCOPE
Qx
LVCMOS
1.65V5%
-1.165V5%
tsk(o)
V
DDOX
2
V
DDOX
2
Qy
Qx
QAx,
QBx,
QCx,
QDx
V
DDOX
2
V
DDOX
2
V
DDOX
2
t
cycle n
t
cycle n+1
tsk(o)
V
DDO
2
V
DDO
2
t()
V
DD
2
V
DD
2
REF_CL:K
FB_IN
Qy
Qx
t
PW
t
PERIOD
V
DDOX
2
V
DDOX
2
V
DDOX
2
t
PW
t
PERIOD
odc =
Clock Outputs
20%
80%
80%
20%
t
R
t
F
QAx, QBx,
QCx, QDx,
FB_OUT
V
DD,
V
DDA,
V
DDOx
GND
GND
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
10
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8761 provides sepa-
r a t e p o w e r s u p p l i e s t o i s o l a t e a n y h i g h s w i t c h i n g
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDOx
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
C2
SPARE
XTAL2
XTAL1
X1
18pF Parallel Cry stal
C1
SPARE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS8761 crystal interface is shown in
Figure 2. While layout
the PC Board, it is recommended to provide C1 and C2 spare
footprints for frequency fine tuning. For an 18pF parallel reso-
F
IGURE
2. C
RYSTAL
I
NPUT
I
NTERFACE
nant crystal, the C1 and C2 are expected to be ~10pF and ~5pF
respectively.
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
11
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
S
CHEMATIC
E
XAMPLE
Figure 3 shows a schematic example of the ICS8761. In this
example, the input is driven by an ICS HiPerClockS LVHSTL
driver. The decoupling capacitors should be physically located
near the power pin. For ICS8761, the unused clock outputs can
be left floating. The optional C1 and C2 are spare footprints for
frequency fine tuning.
F
IGURE
3. ICS8761 C
LOCK
G
ENERATOR
S
CHEMATIC
E
XAMPLE
Receiv er
RU1
1K
(U1,23)
C16
10u
VDDO
C17
0.1u
VDD
SP = Spare, Not Install
(U1,44)
VDD=3.3V
Zo = 50
Zo = 50
C9
0.1u
U1
ICS8761
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
39
38
37
36
35
34
33
32
31
30
29
28
27
52
51
50
49
48
47
46
45
44
43
42
41
40
63
62
61
60
59
58
57
56
55
54
53
64
REF_CLK
GND
XTAL1
XTAL2
VDD
XTAL_SEL
PLL_SEL
VDDA
VDD
D_SELC0
D_SELC1
OEC
OEA
D_SELA0
D_SELA1
GND
GN
D
QA
0
VD
D
O
A
QA
1
GN
D
QA
2
VD
D
O
A
QA
3
GN
D
QB
0
D_SELD0
D_SELD1
OED
OEB
D_SELB0
D_SELB1
GND
QB
3
VD
D
O
B
QB
2
GN
D
QB
1
VD
D
O
B
GN
D
QD
2
VD
D
O
D
QD
3
GND
FB_OUT
VDDOFB
FB_IN
VDD
FBDIV_SEL0
FBDIV_SEL1
MR
VDD
QC
0
VD
D
O
C
QC
1
GN
D
QC
2
VD
D
O
C
QC
3
GN
D
QD
0
VD
D
O
D
QD
1
GN
D
VDD
(U1,46)
Set Logic
Input to '1'
VDDO
VDD
RD1
SP
To Logic
Input pins
R6
1K
C5
0.1u
C12
0.1u
Receiv er
VDDO=3.3V
Set Logic
Input to '0'
C3
0.1u
VDD
R3
36
R5
1K
To Logic
Input pins
C15
0.1u
R4
36
Receiv er
Zo = 50
C13
0.1u
Logic Input Pin Examples
C2
SP
(U1,5)
VDDO
X1
25MHz,18pF
(U1,40)
(U1,19)
C1
SP
RD2
1K
VDDO
C8
0.1u
C11
0.1u
R1
36
C6
0.1u
VDD
(U1,58)
C10
0.1u
Zo = 50
R2
36
(U1,62)
VDD
C14
0.1u
Receiv er
(U1,50)
(U1,9)
(U1,31)
(U1,54)
VDD
C7
0.1u
RU2
SP
R7
10
(U1,27)
C4
0.1u
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
12
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
T
RANSISTOR
C
OUNT
The transistor count for ICS8761 is: 6040
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
64 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
58.8C/W
48.5C/W
43.2C/W
Multi-Layer PCB, JEDEC Standard Test Boards
41.1C/W
35.8C/W
33.6C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
R
ELIABILITY
I
NFORMATION
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
13
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
64 L
EAD
TSSOP
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
N
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8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
14
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
15
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
T
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