Document Outline
- General Description
- Features
- Pin Assignment
- Block Diagram
- Simplified Block Diagram
- Pin Descriptions
- Pin Characteristics
- Output Bank Configuration Select Function Table
- Feedback Configuration Select Function Table
- Control Input Select Function Table
- Timing Diagrams
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- Differential DC Characteristics
- Input Frequency Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Cycle-to-Cycle Jitter Diagram
- Output Skew Diagram
- Static Phase Offset (Differential) Diagram
- Static Phase Offset (LVCMOS) Diagram
- Output Rise/Fall Time Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Application Information
- Using the Output Freeze Circuitry
- Overview
- Protocol
- Freeze Data Input Protocol Diagram
- Output Disable Timing Diagram
- Power Supply
- Wiring the Differential Input to Accept Single Ended Levels
- Differential Clock Input Interface
- HiPerClockS CLK/nCLK Input Driven by ICS HiPerClockS LVHSTL Driver Diagram
- HiPerClockS CLK/nCLK Input Driven by 3.3V LVPECL Driver Diagrams
- HiPerClockS CLK/nCLK Input Driven by 3.3V LVDS Driver Diagram
- Schematic Example
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
87973DYI-147
www.icst.com/products/hiperclocks.html
REV. A AUGUST 26, 2003
1
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
P
IN
A
SSIGNMENT
G
ENERAL
D
ESCRIPTION
The ICS87973I-147 is a LVCMOS/LVTTL clock
generator and a member of the HiPerClockSTM fam-
ily of High Performance Clock Solutions from ICS.
The ICS87973I-147 has three selectable inputs
and provides 14 LVCMOS/LVTTL outputs.
The ICS87973I-147 is a highly flexible device. The three select-
able inputs (1 differential and 2 single ended inputs) are often
used in systems requiring redundant clock sources. Up to three
different output frequencies can be generated among the three
output banks.
The three output banks and feedback output each have their
own output dividers which allows the device to generate a
multitude of different bank frequency ratios and output-to-input
frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3)
can be selected to be inverting or non-inverting. The output fre-
quency range is 10MHz to 150MHz. The input frequency range is
6MHz to 120MHz.
The ICS87973I-147 also has a QSYNC output which can be
used for system synchronization purposes. It monitors Bank A
and Bank C outputs and goes low one period prior to coincident
rising edges of Bank A and Bank C clocks. QSYNC then goes
high again when the coincident rising edges of Bank A and
Bank C occur. This feature is used primarily in applications where
Bank A and Bank C are running at different frequencies, and is
particularly useful when they are running at non-integer mul-
tiples of one another.
Example Applications:
1.
System Clock generator: Use a 16.66MHz reference
clock to generate eight 33.33MHz copies for PCI and
four 100MHz copies for the CPU or PCI-X.
2.
Line Card Multiplier: Multiply differential 62.5MHz from
a back plane to single-ended 125MHz for the line Card
ASICs and Gigabit Ethernet Serdes.
3.
Zero Delay buffer for Synchronous memory: Fan out
up to twelve 100MHz copies from a memory controller
reference clock to the memory chips on a memory module
with zero delay.
F
EATURES
Fully integrated PLL
14 LVCMOS/LVTTL outputs; (12) clock, (1) feedback, (1) sync
Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs
CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 10MHz to 150MHz
VCO range: 240MHz to 500MHz
Output skew: 200ps (maximum)
Cycle-to-cycle jitter, (all banks 4): 55ps (maximum)
Full 3.3V supply voltage
-40C to 85C ambient operating temperature
Pin compatible with MPC973
Compatible with PowerPCTM and PentiumTM Microprocessors
HiPerClockSTM
ICS
FSEL_FB0
V
DD
QFB
GNDO
EXT_FB
QB3
V
DDO
QB2
GNDO
QB1
V
DDO
QB0
GNDO
40
41
42
43
44
45
46
47
48
49
50
51
52
1 2 3 4 5 6 7 8 9 10 11 12 13
26
25
24
23
22
21
20
19
18
17
16
15
14
39 38 37 36 35 34 33 32 31 30 29 28 27
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
V
DDO
QA2
GNDO
QA1
V
DDO
QA0
GNDO
VCO_SEL
FSEL_FB1
QSYNC
GNDO
QC0
V
DDO
QC1
FSEL_C0
FSEL_C1
QC2
V
DDO
QC3
GNDO
INV_CLK
V
DDA
nCLK
CLK
CLK1
CLK0
CLK_SEL
REF_SEL
PLL_SEL
FSEL_FB2
FRZ_D
A
T
A
FRZ_CLK
nMR/OE
GNDI
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
ICS87973I-147
87973DYI-147
www.icst.com/products/hiperclocks.html
REV. A AUGUST 26, 2003
2
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
VCO_SEL
PLL_SEL
REF_SEL
CLK
nCLK
CLK0
CLK1
CLK_SEL
EXT_FB
FSEL_FB2
nMR/OE
FSEL_A0:1
FSEL_B0:1
FSEL_C0:1
FSEL_FB0:2
FRZ_CLK
FRZ_DATA
INV_CLK
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
QFB
QSYNC
OUTPUT DISABLE
CIRCUITRY
DATA GENERATOR
12
2
2
2
3
SYNC PULSE
4, 6, 8, 12
4, 6, 8, 10
2, 4, 6, 8
2
0
1
0
1
0
1
POWER-ON
RESET
PHASE
DETECTOR
VCO
LPF
SYNC
FRZ
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
B
LOCK
D
IAGRAM
1
0
4, 6, 8, 10
87973DYI-147
www.icst.com/products/hiperclocks.html
REV. A AUGUST 26, 2003
3
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
S
IMPLIFIED
B
LOCK
D
IAGRAM
0
1
1
0
0
1
1
2
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
O
UTPUT
D
ISABLE
C
IRCUITRY
0
1
0
1
PLL
VCO R
ANGE
240MHz - 500MHz
SYNC
FRZ
3
2
2
2
INV_CLK
FSEL_A[0:1]
FSEL_B[0:1]
FSEL_C[0:1]
FSEL_FB[0:2]
nMR/OE
0 0 4
0 1 6
1 0 8
1 1 12
FSEL_
A1 A0 QAx
0 0 4
0 1 6
1 0 8
1 1 10
FSEL_
B1 B0 QBx
0 0 0 4
0 0 1 6
0 1 0 8
0 1 1 10
1 0 0 8
1 0 1 12
1 1 0 16
1 1 1 20
FSEL_
FB2 FB1 FB0 QFB
0 0 2
0 1 4
1 0 6
1 1 8
FSEL_
C1 C0 QCx
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
QFB
QSYNC
CLK
nCLK
CLK0
CLK1
CLK_SEL
REF_SEL
EXT_FB
VCO_SEL
PLL_SEL
FRZ_CLK
FRZ_DATA
87973DYI-147
www.icst.com/products/hiperclocks.html
REV. A AUGUST 26, 2003
4
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
T
ABLE
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87973DYI-147
www.icst.com/products/hiperclocks.html
REV. A AUGUST 26, 2003
5
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
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T
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87973DYI-147
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REV. A AUGUST 26, 2003
6
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
fVCO
QA
QC
QSYNC
QA
QC
QSYNC
QC(2)
QA(4)
QSYNC
QC(2)
QA(8)
QSYNC
QC(2)
QA(8)
QSYNC
QA(6)
QC(8)
QSYNC
QA(12)
QC(2)
QSYNC
F
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1. T
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D
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1:1 M
ODE
2:1 M
ODE
3:1 M
ODE
3:2 M
ODE
4:1 M
ODE
4:3 M
ODE
6:1 M
ODE
87973DYI-147
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REV. A AUGUST 26, 2003
7
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
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A
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M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
42.3C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
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87973DYI-147
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REV. A AUGUST 26, 2003
8
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
l
o
b
m
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87973DYI-147
www.icst.com/products/hiperclocks.html
REV. A AUGUST 26, 2003
9
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
C
YCLE
-
TO
-C
YCLE
J
ITTER
O
UTPUT
S
KEW
tsk(o)
V
DDO
2
V
DDO
2
Qy
Qx
S
TATIC
P
HASE
O
FFSET
(D
IFFERENTIAL
)
nCLK
EXT_FB
CLK
t()
V
DD
2
(where
t() is any random sample, and t()
mean
is the average
of the sampled cycles measured on controlled edges)
t ()
mean
= Static Phase Offset
V
CMR
Cross Points
V
PP
nCLK
CLK
GND
V
DD
S
TATIC
P
HASE
O
FFSET
(LVCMOS)
t()
V
DD
2
V
DD
2
(where
t() is any random sample, and t()
mean
is the average
of the sampled cycles measured on controlled edges)
t()
mean
= Static Phase Offset
CLK0,
CLK1
EXT_FB
V
DD
,
V
DDA
, V
DDO
GND
D
IFFERENTIAL
I
NPUT
L
EVEL
QA0:QA3,
QB0:QB3,
QC0:QC3,
QSYNC,
QFB
V
DDO
2
V
DDO
2
V
DDO
2
t
cycle n
t
cycle n+1
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
Clock
Outputs
0.8V
2V
2V
0.8V
t
R
t
F
O
UTPUT
R
ISE
/F
ALL
T
IME
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
QA0:QA3,
QB0:QB3,
QC0:QC3,
QSYNC,
QFB
O
UTPUT
D
UTY
C
YCLE
/ P
ULSE
W
IDTH
P
ERIOD
87973DYI-147
www.icst.com/products/hiperclocks.html
REV. A AUGUST 26, 2003
10
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
FRZ
Latched
FRZ
C
l
o
cke
d
Qx F
REEZE
Internal
Qx Internal
Qx Out
FRZ_CLK
FRZ_DATA
Star
t
Bit
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC1
QC2
QC3 QSYNC
A
PPLICATION
I
NFORMATION
F
IGURE
2A. F
REEZE
D
ATA
I
NPUT
P
ROTOCOL
U
SING
T
HE
O
UTPUT
F
REEZE
C
IRCUITRY
O
VERVIEW
To enable low power states within a system, each output of
ICS87973I-147 (Except QC0 and QFB) can be individually fro-
zen (stopped in the logic "0" state) using a simple serial inter-
face to a 12 bit shift register. A serial interface was chosen to
eliminate the need for each output to have its own Output En-
able pin, which would dramatically increase pin count and pack-
age cost. Common sources in a system that can be used to
drive the ICS87973I-147 serial interface are FPGA's and ASICs.
P
ROTOCOL
The Serial interface consists of two pins, FRZ_Data (Freeze
Data) and FRZ_CLK (Freeze Clock). Each of the outputs which
can be frozen has its own freeze enable bit in the 12 bit shift
register. The sequence is started by supplying a logic "0" start
bit followed by 12NRZ freeze enable bits. The period of each
FRZ_DATA bit equals the period of the FRZ_CLK signal. The
FRZ_DATA serial transmission should be timed so the
ICS87973I-147 can sample each FRZ_DATA bit with the rising
edge of the FRZ_CLK signal. To place an output in the freeze
state, a logic "0" must be written to the respective freeze enable
bit in the shift register. To unfreeze an output, a logic "1" must be
written to the respective freeze enable bit. Outputs will not be-
come enabled/disabled until all 12 data bits are shifted into the
shift register. When all 12 data bits are shifted in the register, the
next rising edge of FRZ_CLK will enable or disable the outputs.
If the bit that is following the 12th bit in the register is a logic "0",
it is used for the start bit of the next cycle; otherwise, the device
will wait and won't start the next cycle until it sees a logic "0" bit.
Freezing and unfreezing of the output clock is synchronous (see
the timing diagram below). When going into a frozen state, the
output clock will go LOW at the time it would normally go LOW,
and the freeze logic will keep the output low until unfrozen. Like-
wise, when coming out of the frozen state, the output will go
HIGH only when it would normally go HIGH. This logic, there-
fore, prevents runt pulses when going into and out of the frozen
state.
F
IGURE
2B. O
UTPUT
D
ISABLE
T
IMING
87973DYI-147
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REV. A AUGUST 26, 2003
11
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87973I-147 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 3 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
pin.
F
IGURE
3. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
Figure 4 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
4. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
87973DYI-147
www.icst.com/products/hiperclocks.html
REV. A AUGUST 26, 2003
12
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
F
IGURE
5C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
5B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
5D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 5A to 5D show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
5A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 5A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
87973DYI-147
www.icst.com/products/hiperclocks.html
REV. A AUGUST 26, 2003
13
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
S
CHEMATIC
E
XAMPLE
Figure 6 shows a schematic example of using ICS87973I-147.
This example shows general design of input, output termination,
logic control input pull up/down and power supply filtering. In
this example, the clock input is driven by an LVCMOS driver.
C8
0.1uF
R3
43
C3
0.1uF
RS
Zo = 50
C11
0.01u
RD1
Not Install
C16
10u
(U1-45)
VDD
C7
0.1uF
RU2
Not Install
VDD
C9
0.1uF
R5
1K
(U1-28)
VDD=3.3V
C6
0.1uF
VDD
(U1-37)
R6
1K
R2
43
Serial Clcok
To Logic
Input
pins
Zo = 50
Set Logic
Input to
'0'
R1
43
To Logic
Input
pins
VDD
R10
1K
C5
0.1uF
R9
1K
(U1-22)
(U1-49)
(U1-33)
Zo = 50
Set Logic
Input to
'1'
U1
ICS87973I-147
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
39
38
37
36
35
34
33
32
31
30
29
28
27
52
51
50
49
48
47
46
45
44
43
42
41
40
GNDI
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2
PLL_SEL
REF_SEL
CLK_SEL
CLK0
CLK1
CLK
nCLK
VDDA
IN
V
_
C
L
K
G
NDO
QC
3
V
DDO
QC
2
F
S
E
L_C
1
F
S
E
L_C
0
QC
1
V
DDO
QC
0
G
NDO
Q
SYN
C
F
S
E
L_F
B
1
GNDO
QB0
VDDO
QB1
GNDO
QB2
VDDO
QB3
EXT_FB
GNDO
QFB
VDD
FSEL_FB0
VC
O
_
SE
L
GN
D
O
QA
0
VD
D
O
QA
1
GN
D
O
QA
2
VD
D
O
QA
3
FS
E
L
_
A
0
FS
E
L
_
A
1
FS
E
L
_
B
0
FS
E
L
_
B
1
VDD
VDD
Logic Input Pin Examples
RD2
1K
R7
10 - 15
(U1-17)
RU1
1K
R8
1K
Serial Data
Zo = 50
R4
1K
C4
0.1uF
LVCMOS CLOCK
VDD
F
IGURE
6. ICS87973I-147 S
CHEMATIC
E
XAMPLE
87973DYI-147
www.icst.com/products/hiperclocks.html
REV. A AUGUST 26, 2003
14
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS87973I-147 is: 8364
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
52 L
EAD
LQFP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
58.0C/W
47.1C/W
42.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
42.3C/W
36.4C/W
34.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
87973DYI-147
www.icst.com/products/hiperclocks.html
REV. A AUGUST 26, 2003
15
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
52 L
EAD
LQFP
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
C
C
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
5
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
2
2
.
0
2
3
.
0
8
3
.
0
c
9
0
.
0
-
-
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87973DYI-147
www.icst.com/products/hiperclocks.html
REV. A AUGUST 26, 2003
16
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
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