Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9158-03
Block Diagram
9158-03 Rev D 7/28/98
Applications
Frequency Generator and Integrated Buffer
The ICS9158-03 is a low-cost frequency generator designed
specifically for desktop and notebook PC applications. Eight
copies of the CPU clock are available.
Each high drive (40mA) output is capable for driving a 30pF
load and has a typical duty cycle of 50/50. The clock
outputs are skew-controlled to within 250ps.
The ICS9158-03 makes a gradual transition between
frequencies, so that it meets the Intel cycle-to-cycle timing
specification for 486 and Pentium systems.
8 skew-free, high drive CPU/BUS clocks
Up to 100 MHz output
250ps skew between all outputs
Outputs can drive up to 30pF load and 40mA
5010% duty cycle
Compatible with 486 and Pentium CPUs
On-chip loop filter components
4.5V - 5.5V supply range
24-pin SOIC package
Ideal for RISC or CISC systems such as 486, Pentium,
PowerPC, etc. requiring multiple CPU and BUS
clocks.
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
2
ICS9158-03
Pin Configuration
24-Pin SOIC
Functionality
(Assuming 14.318 MHz input.)
VDD=5V10% or 3.3V10%, TEMP=0-70C
Peripheral Clocks
FS2
FS1
FS0
CLK2A
(MHz)
CLK12(A-C)
(MHZ)
CLK1(A-D)
(MHz)
0
0
0
32
16
16
0
0
1
32
32
16
0
1
0
32
16
16
0
1
1
32
32
16
1
0
0
50
25
25
1
0
1
50
50
25
1
1
0
66.67
33.33
33.33
1
1
1
60
60
30
OE
CLK2A
CLK12(A-C)
CLK12(A-D)
40MHz
(Pin 6)
24MHz
(Pin 7)
REF
(Pin 18)
1
Runs
Runs
Runs
39.92
23.95
14.31818
0
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
3
ICS9158-03
Pin Descriptions for ICS9158-03
PIN N U M BER
PIN NA M E
TY PE
D ESCR IPTIO N
1
CLK 1A
O U T
CLK 1A clock output
2
X 2
O U T
Crystal connection
3
X 1
IN
Crystal connection
4
V D D
PW R
D igital POW ER SU PPLY (+5V )
5
G N D
PW R
D igital G RO U N D
6
40 M H z
O U T
40 M H z clock output
7
24 M H z
O U T
24 M H z floppy disk/com bination I/O clock output
8
CLK 1B
O U T
CLK 1B clock output
9
AG N D
PW R
A NA LO G G RO U N D
10
O E
IN
O U TPU T ENA B LE. Tristates all outputs w hen low.
11
CLK 12B
O U T
CLK 12B clock output
12
G N D
PW R
D igital G RO U N D
13
CLK 1C
O U T
CLK 1C clock output
14
CLK 1D
O U T
CLK 1D clock output
15
FS2
IN
CPU clock frequency select 2
16
AV D D
PW R
A NA LO G pow er supply (+5V )
17
CLK 12A
O U T
CLK 12A clock output
18
R EF
O U T
14.31818 M H z clock output
19
G N D
PW R
D igital G RO U N D
20
V D D
PW R
D igital POW ER SU PPLY (+5V )
21
CLK 12C
O U T
2X CPU clock output
22
CLK 2A
O U T
CPU clock output
23
FS1
IN
CPU clock frequency select 1
24
FS0
IN
CPU clock frequency select 0
4
ICS9158-03
Electrical Characteristics at 5V
Absolute Maximum Ratings
AVDD, VDD referenced to GND . . . . . . . . . . . . . . . . 7V
Operating temperature under bias. . . . . . . . . . . . . . . . 0C to +70C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +150C
Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
DC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Voltage
V
IL
0.8
V
Input High Voltage
V
IH
2.0
V
Input Low Current
I
IL
V
IN
=0V (Pull-up)
-20
A
Input High Current
I
IH
V
IN
=V
DD
-5
5
A
Output Low Voltage
V
OL
I
OL
=20.0mA
0.25
0.4
V
Output High Voltage
1
V
OH
I
OH
=-30mA
2.4
3.5
V
Output Low Current
1
I
OL
V
OL
=0.8V
45
65
mA
Output High Current
1
I
OH
V
OH
=2.0V
-55
-35
mA
Supply Current
I
DD
No load, 66 MHz
67
100
mA
Output Frequency Change over
Supply and Temperature
1
F
D
With respect to typical
frequency
0.002
0.01
%
Short circuit current
1
I
SC
Each output clock
25
56
mA
Pull-up resistor value
1
R
PU
Input pin
680
k
Input Capacitance
1
C
i
Except X1, X2
8
pf
Load Capacitance
1
C
L
Pins X1, X2
20
pf
V
DD
= +5V10%, T
A
=0C to 70C unless otherwise stated
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
5
ICS9158-03
Electrical Characteristics (
continued)
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
AC Characteristics
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNITS
Output Rise time, 0.8 to 2.0V (Note 1)
tr
30pf load
-
1
2.0
ns
Rise time, 20% to 80% VDD (Note 1)
tr
30pf load
-
2.5
3
ns
Output Fall time, 2.0 to 0.8V
1
tf
30pf load
-
0.5
2.0
ns
Fall time, 80% to 20% VDD
1
tf
30pf load
-
1.5
3.0
ns
Duty cycle
1
dt
30pf load
45/55
48/52
55/45
%
Jitter, one sigma
1
tj1s
As compared with
clock period
0.5
2.0
%
Jitter, absolute
tjab
-5
2
5
%
Jitter, absolute
tjab
25-66MHz clocks
-250
250
ps
Input Frequency
fi
14.318
MHz
Clock skew between CLK2A,
CLK1(A-D) and CLK12(A-C) outputs
Tsk
-250
100
250
ps
Frequency Transition Time
1
tft
From 4 to 50 MHz
13
20
ms
V
DD
= +5V10%, T
A
=0C to 70C unless otherwise stated
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