/home/web/doc/html/icst/173735

Integrated

Circuit

Systems, Inc.

General Description

Features

ICS9179B-01

Block Diagram

PentiumPro is a trademark of Intel Corporation

C is a trademark of Philips Corporation

Low Skew Buffers

9179B-01 Rev C 05/18/98

Pin Configuration

The ICS9179B-01 generates SDRAM clock buffers required

for high speed RISC or CISC microprocessor systems such as

Intel PentiumPro or Pentium II. An output enable is provided

for testability.

The device is a buffer with low output to output skew. This is

a Fanout buffer device, not using an internal PLL. This buffer

can also be a feedback to an external PLL stage for phase

synchronization to a master clock.

The individual clock outputs are addressable through I

C to

be enabled, or stopped in a low state for reduced EMI when

the lines are not needed.

High speed, low noise non-inverting (0:17) buffer for

SDRAM clock buffer applications.

Supports up to four SDRAM DIMMS

Synchronous clocks skew matched to 250ps window on

SDRAM.

C Serial Configuration interface to allow individual

clocks to be stopped.

Multiple VDD, VSS pins for noise reduction

Tri-state pin for testing

Custom configurations available

3.0V 3.7V supply range

48-pin SSOP package

48-Pin SSOP

ICS reserves the right to make changes in the device data identified in this

publication without further notice. ICS advises its customers to obtain the latest

version of all device data to verify that any information being relied upon by the

customer is current and accurate.

ICS9179B-01

Pin Descriptions

Power Groups

VDD = Power supply for SDRAM buffer

VDDS = Power supply for I

C circuitry

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

4, 5, 8, 9

SDRAM (0:3)

OUT

SDRAM Byte 0 clock outputs

13, 14, 17, 18

SDRAM (4:7)

OUT

SDRAM Byte 1 clock outputs

31, 32, 35, 36

SDRAM (8:11)

OUT

SDRAM Byte 2 clock outputs

40, 41, 44, 45

SDRAM (12:15)

OUT

SDRAM Byte 3 clock outputs

21, 28

SDRAM (16:17)

OUT

SDRAM clock outputs useable for feedback.

BUF_IN

Input for buffers

Tri-states all outputs when held LOW. Has internal pull-up.

SDATA

I/O

Data pin for I

C circuitry

SCLK

I/O

Clock pin for I

C circuitry

3, 7, 12, 16, 20,

29, 33, 37, 42, 46

VDD

PWR

3.3V Power supply for SDRAM buffer

6, 10, 15, 19, 22,

27, 30, 34, 39, 43

GND

PWR

Ground for SDRAM buffer

VDDS

PWR

3.3V Power supply for I

C circuitry

GNDS

PWR

Ground for I

C circuitry

1, 2, 47, 48

N/C

Pins are not internally connected

Notes:
1.

At power up all eighteen SDRAM outputs are enabled and active.

OE has a 100K Ohm internal pull-up resistor to keep all outputs active.

The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for

complete platform flexibility.

Ground Groups

GND = Ground for SDRAM buffer

GNDS = Ground for I

C circuitry

ICS9179B-01

VDD

This is the power supply to the internal core logic of the

device as well as the clock output buffers for SDRAM(0:17).

This pin operates at 3.3V volts. Clocks from the listed buffers

that it supplies will have a voltage swing from Ground to this

level. For the actual guaranteed high and low voltage levels

for the Clocks, please consult the DC parameter table in this

data sheet.

GND

This is the power supply ground (common or negative) return

pin for the internal core logic and all the output buffers.

SDRAM(0:17)

These Output Clocks are use to drive Dynamic RAMs and

are low skew copies of the CPU Clocks. The voltage swing of

the SDRAMs output is controlled by the supply voltage

that is applied to VDD of the device, operates at 3.3 volts.

The SDATA and SCLOCK Inputs are use to program the

device. The clock generator is a slave-receiver device in the

C protocol. It will allow read-back of the registers. See

configuration map for register functions. The I

specification in Philips I

C Peripherals Data Handbook (1996)

should be followed.

BUF_IN

Input for Fanout buffers (SDRAM 0:17).

OE tristates all outputs when held low.

VDDS

This is the power supply to I

C circuitry.

GNDS

This is the ground to I

C circuitry.

Technical Pin Function Descriptions

ICS9179B-01

Serial Configuration Command Bitmaps

Byte 0: SDRAM Clock Register

For the clock generator to be addressed by an I

C controller, the following address must be sent as a start sequence, with

an acknowledge bit between each byte.

The clock generator is a slave/receiver I

C component. It can "read back "(in Philips I

C protocol) the data stored in the

latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB

PIIX4 protocol.

The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)

The input is operating at 3.3V logic levels.

The data byte format is 8 bit bytes.

To simplify the clock generator I

C interface, the protocol is set to use only block writes from the controller. The bytes

must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has

been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two

bytes. The data is loaded until a Stop sequence is issued.

In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches

maintain all prior programming information.

At power-on, all registers are set to a default condition. Bytes 0 through 2 default to a 1 (Enabled output state).

General I

C serial interface information

Notes: 1 = Enabled; 0 = Disabled, outputs held low

Then Byte 0, 1, 2, etc in

sequence until STOP.

Clock Generator

Address (7 bits)

ACK

+ 8 bits dummy

command code

ACK

+ 8 bits dummy

Byte count

ACK

A(6:0) & R/W#

(H)

BIT

PIN#

PWD

DESCRIPTION

Bit7

SDRAM7 (Act/Inact)

Bit6

SDRAM6 (Act/Inact)

Bit5

SDRAM5 (Act/Inact)

Bit4

SDRAM4 (Act/Inact)

Bit3

SDRAM3 (Act/Inact)

Bit2

SDRAM2 (Act/Inact)

Bit1

SDRAM1 (Act/Inact)

Bit0

SDRAM0 (Act/Inact)

Byte 0, 1, 2, etc in sequence until STOP.

Clock Generator

Address (7 bits)

ACK

Byte 0

ACK

Byte 1

ACK

A(6:0) & R/W#

(H)

Note: PWD = Power-Up Default

ICS9179B-01

Byte 1: SDRAM Clock Register

Functionality

Notes: 1 = Enabled; 0 = Disabled, outputs held low

Byte 2: PCICLK Clock Register

Notes: 1 = Enabled; 0 = Disabled, outputs held low

BIT

PIN#

PW D

DESCRIPTION

Bit 7

SDRAM17 (Act/Inact)

Bit 6

SDRAM16 (Act/Inact)

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Bit 0

Reserved

OE#

SDRAM (0:3)

SDRAM (4:7)

SDRAM (8:11)

SDRAM (12:15)

SDRAM (16:17)

Hi-Z

1 X BUF_IN

BIT

PIN#

PWD

DESCRIPTION

Bit 7

SDRAM15 (Act/Inact)

Bit 6

SDRAM14 (Act/Inact)

Bit 5

SDRAM13 (Act/Inact)

Bit 4

SDRAM12 (Act/Inact)

Bit 3

SDRAM11 (Act/Inact))

Bit 2

SDRAM10 (Act/Inact)

Bit 1

SDRAM9 (Act/Inact)

Bit 0

SDRAM8 (Act/Inact))

ICS9179B-01 Power Management

The values below are estimates of target specifications.

Condition

Max 3.3V supply consumption
Max discrete cap loads
VDD = 3.465V
All static inputs = VDD or GND

No Clock Mode
(BUF_IN - VDD1 or GND)
I

C Circuitry Active

3mA

Active 66MHz
(BUF_IN = 66.66MHz)

115mA

Active 100MHz
(BUF_IN = 100.00MHz)

180mA

Note: PWD = Power-Up Default

Электронный компонент: ICS9179