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Электронный компонент: ICS9248-175

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9250-08
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Integrated
Circuit
Systems, Inc.
ICS9248-175
Third party brands and names are the property of their respective owners.
Block Diagram
9248-175 Rev - 9/11/00
Advance Information
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
VIA KX133 style chipset
Output Features:
1 - Differential pair open drain CPU clocks @ 3.3V
1 - Single-ended open drain CPU clock @ 3.3V
13 - SDRAM @ 3.3V
6 - PCI @3.3V,
1 - 48MHz, @3.3V fixed.
1 - 24/48MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
Features:
Up to 166MHz frequency support
Support power management: CPU stop and Power down
Mode from I
2
C programming.
Spread spectrum for EMI control
( 0.25% center spread).
Uses external 14.318MHz crystal
AMD - K7
System Clock Chip
* Internal Pull-up Resistor of 120K to VDD
VDD
REF0/CPU_STOP#*
GND
X1
X2
VDD2
MODE*/PCICLK0
FS1*/PCICLK1
GND
PCICLK2
PCICLK3
PCICLK4
PCICLK5
VDD2
BUFFER_IN
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLK
REF1/FS0*
GND
CPUCLKT1
GND
CPUCLKC0
CPUCLKT0
VDDA
PD#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
VDD4
48MHz/FS2*
24_48MHz/FS3*
ICS9248-175
1
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BUFFER IN
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
SDRAM (11:0)
PCICLK (5:0)
SDRAM_OUT
CPUCLKT (1:0)
CPUCLKC0
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
SDATA
SCLK
FS (3:0)
PD#
CPU_STOP#
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
SDRAM
DRIVER
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2
ICS9248-175
Advance Information
Third party brands and names are the property of their respective owners.
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
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background image
3
ICS9248-175
Advance Information
Third party brands and names are the property of their respective owners.
General Description
The ICS9248-175 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all
clocks required for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-175 employs
a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
7
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Power Groups
VDD4 = 48MHz, PLL2
VDDA = VDD for Core PLL
VDD = REF, Xtal
background image
4
ICS9248-175
Advance Information
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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5
2
.
0
0
1
1
1
1
0
.
3
1
1
6
.
7
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
1
0
0
0
0
0
.
2
1
1
3
.
7
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
1
0
0
0
1
0
.
1
1
1
0
.
7
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
1
0
0
1
0
0
.
0
1
1
6
.
6
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
1
0
0
1
1
0
.
9
0
1
3
.
6
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
1
0
1
0
0
0
.
8
0
1
0
.
6
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
1
0
1
0
1
0
.
7
0
1
6
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
1
0
1
1
0
0
.
6
0
1
3
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
1
0
1
1
1
0
.
4
0
1
6
.
4
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
1
1
0
0
0
0
.
2
0
1
0
.
4
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
1
1
0
0
1
3
.
3
3
1
3
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
0
5
.
0
1
1
0
1
0
3
.
3
3
1
3
.
3
3
d
a
e
r
p
S
r
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t
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C
%
5
2
.
0
1
1
0
1
1
3
.
3
3
1
3
.
3
3
d
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w
o
D
0
5
.
0
-
1
1
1
0
0
0
.
5
9
7
.
1
3
d
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%
5
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1
1
1
0
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0
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0
0
1
3
.
3
3
d
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0
5
.
0
1
1
1
1
0
0
.
0
0
1
3
.
3
3
d
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r
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C
%
5
2
.
0
1
1
1
1
1
0
.
0
0
1
3
.
3
3
d
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0
5
.
0
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3
t
i
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t
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4
:
7
,
2
t
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B
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7
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m
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d
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-
0
l
a
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N
-
1
1
0
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B
g
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R
-
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-
1
0
background image
5
ICS9248-175
Advance Information
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
#
0
S
F
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
-
0
#
1
S
F
3
t
i
B
0
4
1
T
U
O
_
M
A
R
D
S
2
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B
3
4
,
4
4
1
O
T
K
L
C
U
P
C
,
0
C
K
L
C
U
P
C
.
r
i
a
p
l
a
i
t
n
e
r
e
f
f
i
d
h
t
o
b
(
e
l
b
a
n
e
)
"
y
r
a
t
n
e
m
i
l
p
m
o
C
d
n
a
"
e
u
r
T
"
0
t
i
B
6
4
1
e
l
b
a
n
e
1
T
K
L
C
U
P
C
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
#
2
S
F
6
t
i
B
7
1
0
K
L
C
I
C
P
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
3
1
1
5
K
L
C
I
C
P
3
t
i
B
2
1
1
4
K
L
C
I
C
P
2
t
i
B
1
1
1
3
K
L
C
I
C
P
1
t
i
B
0
1
1
2
K
L
C
I
C
P
0
t
i
B
8
1
1
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
0
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
Byte 4: Reserved, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
-
1
#
E
D
O
M
3
t
i
B
-
0
#
3
S
F
2
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B
8
4
1
1
F
E
R
0
t
i
B
2
1
0
F
E
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Reserved, Active/Inactive Register
(1= enable, 0 = disable)
Note: Don't write into this register, writing into this register
can cause malfunction
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B
-
0
z
H
M
8
4
_
L
E
S
5
t
i
B
6
2
1
z
H
M
8
4
4
t
i
B
5
2
1
z
H
M
8
4
_
4
2
3
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B
,
0
2
,
7
1
1
2
1
)
8
:
1
1
(
M
A
R
D
S
1
t
i
B
,
9
2
,
8
2
2
3
,
1
3
1
)
4
:
7
(
M
A
R
D
S
0
t
i
B
,
5
3
,
4
3
8
3
,
7
3
1
)
0
:
3
(
M
A
R
D
S