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Электронный компонент: ICS9248-96

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Integrated
Circuit
Systems, Inc.
ICS9248-96
Third party brands and names are the property of their respective owners.
Block Diagram
9248- 96 Rev A 2/7/00
Recommended Application:
810/810E type chipset.
Output Features:
2- CPUs @ 2.5V, up to 155MHz.
9 - SDRAM @ 3.3V, up to 155MHz including
1 free running
8 - PCICLK @ 3.3V
1 - IOAPIC @ 2.5V,
2 - 3V66MHz @ 3.3V, 2X PCI MHz
2 - 48MHz, @ 3.3V fixed.
1 - 24/48MHz, @3.3V selectable by I
2
C
1 - REF @v3.3V, 14.318MHz.
Features:
Up to 157MHz frequency support
Support FS0-FS3 strapping status bit for I
2
C read back.
Support power management: Through Power down
Mode from I
2
C programming.
Spread spectrum for EMI control ( 0.25% center).
Uses external 14.318MHz crystal
Skew Specifications:
CPU CPU: <175ps
SDRAM - SDRAM: < 250ps
3V66 3V66: <175ps
PCI PCI: <500ps
CPU-SDRAM<500ps
For group skew specifications, please refer to group
timing relationship.
Functionality
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD.
** 60K pull-up to VDD on indicated input
1 These are double strength.
Frequency Generator & Integrated Buffers for Celeron & P
II
/
III
TM
Additional frequencies selectable through I
2
C programming.
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3
Preliminary Product Preview
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
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2
ICS9248-96
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
General Description
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
FREQ_IOAPIC
IN
If FREQ_APIC = 0, APIC Clock = PCICLK
If FREQ_APIC = 1, APIC Clock = PCICLK/2 (default)
REF0
OUT
14.318 MHz reference clock.
2, 9, 10, 18, 25, 30,
38
VDD
PWR
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
3
X1
IN
Crystal input,nominally 14.318MHz.
4
X2
OUT
Crystal output, nominally 14.318MHz.
5, 6, 14, 21, 29, 34,
42
GND
PWR
Ground pin for 3V outputs.
8, 7
3V66 [1:0]
OUT
3.3V Clocks
FS0
IN
Frequency select pin.
PCICLK0
OUT
PCI clock output
FS1
IN
Frequency select pin.
PCICLK1
OUT
PCI clock output
SEL24_48MHz#
IN
Logic inputs frequency select I/O/USB output,
When a "0" is latched, output frequency = 48MHz
When a "1" is latched, output frequency = 24MHz
PCICLK2
OUT
PCI clock output
20, 19, 17, 16, 15
PCICLK [7:3]
OUT
PCI clock outputs.
22
PD#
IN
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
23
SCLK
IN
Clock input of I2C input, 5V tolerant input
24
SDATA
IN
Data input for I2C serial input, 5V tolerant input
FS3
IN
Frequency select pin.
48MHz_0
OUT
48MHz output clocks
27
48MHz_1
OUT
48MHz output clocks
FS2
IN
Frequency select pin.
24_48MHz
OUT
24 or 48MHz output
31
SDRAM_F
OUT
Free running SDRAM - used for feed back to chipset, should remain on
always.
32, 33, 35, 36, 37,
39, 40, 41,
SDRAM [7:0]
OUT
SDRAM clock outputs
43
GNDLCPU
PWR
Ground pin for the CPU clocks.
44, 45
CPUCLK [1:0]
OUT
CPU clock outputs.
46
VDDLCPU
PWR
Power pin for the CPUCLKs. 2.5V
47
IOAPIC
OUT
2.5V clock output
48
VDDLAPIC
PWR
Power pin for the IOAPIC. 2.5V
1
26
28
11
12
13
Power Groups
GNDREF, VDDREF = REF0, X1, X2
GNDPCI , VDDPCI = PCICLK [9:0]
GNDSDR, VDDSDR = SDRAM [7:0], SDRAM_F,
supply for PLL core
GND3V66 , VDD3V66 = 3V66
GND48 , VDD48 = 48MHz, 24_48MHz,
VDDLAPIC = IOAPIC
GNDLCPU , VDDLCPU = CPUCLK [1:0]
The ICS9248-96 is the single chip clock solution for designs
using the 810/810E style chipset. It provides all necessary
clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-96
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection.
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3
ICS9248-96
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Write:
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4
ICS9248-96
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
* These frequencies with spread enabled are equal to original Intel defined frequency with -0.5% down spread.
I
2
C is a trademark of Philips Corporation
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5
2
.
9
6
3
6
.
4
3
1
3
.
7
1
3
6
.
4
3
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
1
1
0
0
0
.
0
7
0
0
.
5
0
1
0
0
.
0
7
0
0
.
5
3
0
5
.
7
1
0
0
.
5
3
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
1
1
1
7
6
.
6
7
0
0
.
5
1
1
7
6
.
6
7
3
3
.
8
3
7
1
.
9
1
3
3
.
8
3
r
e
t
n
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C
%
5
2
.
0
-
/
+
1
1
0
0
0
0
0
.
5
4
1
0
0
.
5
4
1
7
6
.
6
9
3
3
.
8
4
7
1
.
4
2
3
3
.
8
4
r
e
t
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C
%
5
2
.
0
-
/
+
1
1
0
0
1
0
5
.
6
6
5
7
.
9
9
0
5
.
6
6
5
2
.
3
3
3
6
.
6
1
5
2
.
3
3
r
e
t
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C
%
5
2
.
0
-
/
+
1
1
0
1
0
0
0
.
0
5
1
0
0
.
0
5
1
0
0
.
0
0
1
0
0
.
0
5
0
0
.
5
2
0
0
.
0
5
*
r
e
t
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C
%
5
2
.
0
-
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+
1
1
0
1
1
5
7
.
9
9
5
7
.
9
9
0
5
.
6
6
5
2
.
3
3
3
6
.
6
1
5
2
.
3
3
*
r
e
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C
%
5
2
.
0
-
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+
1
1
1
0
0
0
0
.
5
5
1
0
0
.
5
5
1
3
3
.
3
0
1
7
6
.
1
5
3
8
.
5
2
7
6
.
1
5
r
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C
%
5
2
.
0
-
/
+
1
1
1
0
1
0
5
.
6
6
1
0
5
.
6
6
1
0
0
.
1
1
1
0
5
.
5
5
5
7
.
7
2
0
5
.
5
5
r
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t
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C
%
5
2
.
0
-
/
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1
1
1
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0
3
3
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3
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1
0
0
.
5
1
1
7
6
.
6
7
3
3
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9
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5
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1
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7
.
9
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3
t
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B
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t
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a
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y
b
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q
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r
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-
0
4
:
7
,
2
t
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B
y
b
d
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t
c
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l
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s
s
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y
c
n
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r
F
-
1
0
1
t
i
B
l
a
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r
o
N
-
0
d
a
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r
p
S
r
e
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C
%
5
2
.
0
d
e
l
b
a
n
E
m
u
r
t
c
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p
S
d
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e
r
p
S
-
1
1
0
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B
g
n
i
n
n
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R
-
0
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t
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-
1
0
background image
5
ICS9248-96
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
Byte 1: Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
#
3
S
F
6
t
i
B
-
X
#
0
S
F
5
t
i
B
-
X
#
2
S
F
4
t
i
B
8
2
1
z
H
M
8
4
_
4
2
3
t
i
B
7
2
1
1
_
z
H
M
8
4
2
t
i
B
6
2
1
0
_
z
H
M
8
4
1
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
0
t
i
B
1
3
1
F
_
M
A
R
D
S
Byte 4: Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B
8
1
1
_
6
6
V
3
5
t
i
B
7
1
0
_
6
6
V
3
4
t
i
B
-
X
#
C
I
P
A
O
I
_
Q
E
R
F
3
t
i
B
6
4
1
C
I
P
A
O
I
2
t
i
B
-
X
#
1
S
F
1
t
i
B
4
4
1
1
K
L
C
U
P
C
0
t
i
B
5
4
1
0
K
L
C
U
P
C
Byte 3: PCI, Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
0
2
1
7
K
L
C
I
C
P
6
t
i
B
9
1
1
6
K
L
C
I
C
P
5
t
i
B
7
1
1
5
K
L
C
I
C
P
4
t
i
B
6
1
1
4
K
L
C
I
C
P
3
t
i
B
5
1
1
3
K
L
C
I
C
P
2
t
i
B
3
1
1
2
K
L
C
I
C
P
1
t
i
B
2
1
1
1
K
L
C
I
C
P
0
t
i
B
1
1
1
0
K
L
C
I
C
P
Byte 2: SDRAM, Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
2
3
1
7
M
A
R
D
S
6
t
i
B
3
3
1
6
M
A
R
D
S
5
t
i
B
5
3
1
5
M
A
R
D
S
4
t
i
B
6
3
1
4
M
A
R
D
S
3
t
i
B
7
3
1
3
M
A
R
D
S
2
t
i
B
9
3
1
2
M
A
R
D
S
1
t
i
B
0
4
1
1
M
A
R
D
S
0
t
i
B
1
4
1
0
M
A
R
D
S
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Dont write into this register, writing into this
register can cause malfunction