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Электронный компонент: ICS9248F-151-T

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Integrated
Circuit
Systems, Inc.
ICS9248-151
Third party brands and names are the property of their respective owners.
Block Diagram
9248-151 Rev B 01/29/01
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
VIA Apollo Pro 266 style chipset.
Output Features:
3 - CPUs @ 2.5V, up to 200MHz.
3 - IOAPIC @ 2.5V, PCI frequency
9 - PCI @ 3.3V,
1 - 48MHz, @ 3.3V fixed.
1 - 24/48MHz @ 3.3V
2 - REF @ 3.3V, 14.318MHz.
3 - AGP @ 3.3V
Features:
Up to 200MHz frequency support
Support power management: PCI, CPU stop
and Power Down.
Spread spectrum for EMI control (0 to -0.5%, 0.25%).
Uses external 14.318MHz crystal
Skew Specifications:
CPU CPU: <175ps
PCI PCI: <500ps
CPU(early)-PCI: Min=1.0ns, Max=2.5ns
CPU Cycle to cycle jitter: < 250ps
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
* Internal Pull-up Resistor of 120K to VDD
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
SDATA
SCLK
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK (1:0)
CPUCLK2/F
IOAPIC (2:0)
AGPCLK (2:0)
PCICLK (7:0)
8
3
3
2
2
PCICLK_F
X1
X2
XTAL
OSC
CPU
DIVDER
IOAPIC
DIVDER
AGP
DIVDER
PCI
DIVDER
Stop
Stop/F
Stop
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
4
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VDDREF
GND
X1
X2
AVDD48
*FS3/48MHz
*FS2/24_48MHz
GND
PCICLK_F
PCICLK0
PCICLK1
GND
PCICLK2
PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
*FS1
*FS0
AGPCLK0
VDDAGP
REF0
REF1/FS4*
VDDLAPIC
IOAPIC0
IOAPIC1
GND
IOAPIC2
VDDLCPU
GND
CPUCLK0
CPUCLK1
VDDLCPU
GND
CPUCLK2/F
CPU_STOP#*
PCI_STOP#*
PD*
AVDD
GND
SDATA
SCLK
AGPCLK2
AGPCLK1
GND
ICS9248-151
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS9248-151
Third party brands and names are the property of their respective owners.
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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3
ICS9248-151
Third party brands and names are the property of their respective owners.
General Description
The ICS9248-151 is a single chip clock solution for Desktop
designs. It provides all necessary clock signals for such a
system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-151
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection.
Power Groups
AVDD, AGND = Core PLL
AVDD48, AGND48 = 24, 48MHz and fixed PLL
VDDREF, GNDREF = REF clocks, Xtal
4
ICS9248-151
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note1: Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3.
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4
:
6
[
1
,
2
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5
ICS9248-151
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
0
2
1
7
K
L
C
I
C
P
6
t
i
B
8
1
1
6
K
L
C
I
C
P
5
t
i
B
7
1
1
5
K
L
C
I
C
P
4
t
i
B
6
1
1
4
K
L
C
I
C
P
3
t
i
B
4
1
1
3
K
L
C
I
C
P
2
t
i
B
3
1
1
2
K
L
C
I
C
P
1
t
i
B
1
1
1
1
K
L
C
I
C
P
0
t
i
B
0
1
1
0
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
0
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
4
4
1
1
C
I
P
A
O
I
4
t
i
B
5
4
1
0
C
I
P
A
O
I
3
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B
7
4
1
1
F
E
R
0
t
i
B
8
4
1
0
F
E
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
ti
B
-
X
#
2
S
F
6
ti
B
-
0
8
4
_
4
2
L
E
S
z
H
M
8
4
=
1
z
H
M
4
2
=
0
5
ti
B
6
1
z
H
M
8
4
4
ti
B
7
1
z
H
M
8
4
_
4
2
3
ti
B
9
1
F
_
K
L
C
I
C
P
2
ti
B
7
2
1
2
K
L
C
P
G
A
1
ti
B
6
2
1
1
K
L
C
P
G
A
0
ti
B
3
2
1
0
K
L
C
P
G
A
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Don't write into this register, writing into this
register can cause malfunction
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
5
3
0
;
#
F
U
P
C
_
L
E
S
g
n
i
n
n
u
r
e
e
r
f
e
b
l
l
i
w
2
K
L
C
U
P
C
=
0
g
n
i
n
n
u
r
e
e
r
f
e
b
t
o
n
l
l
i
w
2
K
L
C
U
P
C
=
1
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
X
#
4
S
F
4
t
i
B
-
X
#
3
S
F
3
t
i
B
5
3
1
2
K
L
C
U
P
C
2
t
i
B
8
3
1
1
K
L
C
U
P
C
1
t
i
B
9
3
1
0
K
L
C
U
P
C
0
t
i
B
2
4
1
2
C
I
P
A
O
I