Integrated
Circuit
Systems, Inc.
ICS9248- 131
Block Diagram
Pentium is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
9248-131 Rev B 7/17/00
Pin Configuration
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
VDDF
*REF0/CPU2.5_3.3#
GND
X1
X2
VDDPCI
*PCICLK_F/FS1
*PCICLK0/FS2
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDA
BUFFERIN
GND
*CPU_STOP#/SDRAM11
*PCI_STOP#/SDRAM10
VDDSDR
*AGP_STOP#/SDRAM9
*PD#/SDRAM8
GND
SDATA
SCLK
VDDAGP
AGP0
AGP1
GND
CPUCLK0
CPUCLK1
VDDL
CPUCLK2
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
48MHz/FS0*
AGP_F/MODE*
SDRAM12
GND
ICS9248-131
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Recommended Application:
ALI - Aladdin V
- mobile style chipsets
Output Features:
3 - CPUs @ 2.5/3.3V, up to 100MHz.
3 - AGPCLK @ 3.3V
13 - SDRAM @ 3.3V
6 - PCI @ 3.3V
1 - 48MHz, @ 3.3V fixed.
1 - REF @ 3.3V, 14.318MHz.
Features:
Support power management: CPU, PCI, AGP stop and
Power down Mode from I
2
C programming.
Spread spectrum for EMI control.
Uses external 14.318MHz crystal
FS pins for frequency select
Key Specifications:
CPU CPU: <250ps
AGP PCI: <550ps
CPU(early)-PCI: 1-4ns, Center 2-6ns
Frequency Generator & Integrated Buffers for Celeron & P
II
/
III
TM
CPU2.5_3.3#
PLL2
PLL1
Spread
Spectrum
48MHz
CPUCLK (2:0)
PCICLK (4:0)
AGP (1:0)
2
5
3
AGP_F
PCICLK_F
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
AGP
DIVDER
Stop
Stop
Stop
SDATA
SCLK
FS (2:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
AGP-STOP#
MODE
Control
Logic
Config.
Reg.
REF
BUFFERIN
SDRAM (12:0)
13
1
1
1
100
33.33
66.67
1
1
0
95.25
31.75
63.50
1
0
1
83.3
33.30
66.60
1
0
0
97
32.33
64.66
0
1
1
91.5
30.50
61.00
0
1
0
96.22
32.07
64.15
0
0
1
66.67
33.33
66.67
0
0
0
60
30.00
60.00
PCI
(MHz)
FS2
FS1
FS0
CPU, SDRA M
(MHz)
AGP
(MHz)
Functionality
Note: REF & IOAPIC = 14.318MHz
Power Groups
Analog
Digital
VDDF
VDDPCI
VDDA
VDDSDR
VDDAGP
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS9248- 131
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
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CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
Power Management Functionality
Mode Pin - Power Management Input Control
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General Description
The ICS9248-131 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro
or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-131 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection. The SDRAM12
output may be used as a feed back into an off chip PLL.
4
ICS9248- 131
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
I
2
C is a trademark of Philips Corporation
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 001, and if bit
3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle.
Note: PWD = Power-Up Default
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
t
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6
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I
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P
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
PWD
Bit7 Bit2
0,0
0,1
1,0
1,1
Bit6 Bit5 Bit4
CPU Clock
PCI
AGP
111
100
33.33
66.67
110
95.25
31.75
63.50
101
83.3
33.30
66.60
100
97
32.33
64.66
011
91.5
30.50
61.00
010
96.22
32.07
64.15
001
66.67
33.33
66.67
000
60
30.00
60.00
Bit 1
Bit 0
1 - Tristate all outputs
0 - Frequency is selected by hardware select, Latched inputs
1 - Frequency is selected by Bit 6:4 (above)
0 to -0.5 Down Spread Spectrum Modulation
+/- 0.375% Center Spread Spectrum Modulation
0
0
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
Description
Note1
001
Bit 3
Bit 6:4
Bit 7,2
0,0
Spread Spectrum Method
+/- 0.25% Center Spread Spectrum Modulation
+/- 0.15% Center Spread Spectrum Modulation
0
5
ICS9248- 131
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
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Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
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0
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2
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(
0
F
E
R
Byte 6: Optional Register for Possible
Furture Requirements
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for futue
applications.
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5
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(
4
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d
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3
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2
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1
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(
0
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