Integrated
Circuit
Systems, Inc.
ICS9248- 195
0375D--02/02/04
Block Diagram
Frequency Generator & Integrated Buffers for PENTIUM
II
/
III
TM
& K6
Pin Configuration
48-Pin SSOP and TSSOP
* Internal Pull-up Resistor of 120K to VDD
VDDREF
*SPREAD/REF0
GNDREF
X1
X2
VDDPCI
*CPU2.5_3.3#/PCICLK_F
*FS3/PCICLK0
GNDPCI
*SEL24_48#/PCICLK1
*SELPCIE_6#/PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GNDPCI
PCICLK5
PCICLK6/
VDDCOR
PCI_STOP#
*Vtt_PWRGD/PD#
GND48
SDATA
SCLK
PCICLK_E
REF1/FS2*
VDDLCPU
CPUCLK_F
CPUCLK0
GNDLCPU
CPUCLK1
CPUCLK2
CLK_STOP#
GNDSDR
SDRAM_F
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GNDSDR
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24_48MHz/FS1*
ICS9248-195
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Recommended Application:
440BX, MX, VIA PM/PL/PLE 133 style chip set, with
Coppermine or Tualatin processor, for note book
applications.
Output Features:
4 - CPUs @ 2.5V/3.3V
including 1 free running CPUCLK_F
9 - SDRAM @ 3.3V
7 - PCI @ 3.3V, including 1 free running PCICLK_F
1 - PCI Early @ 3.3V
1 - 48MHz, @ 3.3V fixed.
1 - 24/48MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
Features:
Up to 137MHz frequency support
97MHz to support high-end AMD processor.
Support power management: CLK, PCI, stop and
Power down Mode from I
2
C programming.
Spread spectrum for EMI control
Uses external 14.318MHz crystal
FS pins for frequency select
Functionality
2
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3
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3
Key Specifications:
CPU Output Jitter @ 2.5V: <300ps
CPU Output Jitter @ 3.3V: <250ps
PCI Output Jitter @ 3.3V: <250ps
CPU Output Skew @ 2.5V: <175ps
CPU Output Skew @ 3.3V: <175ps
PCI Output Skew @ 3.3V: <500ps
PCI Early to PCI Skew @ 3.3V: typ = 3ns
SDRAM Output Skew @ 3.3V: <500ps
2
ICS9248-195
0375D--02/02/04
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
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3
ICS9248-195
0375D--02/02/04
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Notes:
1, Default at Power-up will be for latched logic inputs to define frequency. Bit [2, 6:4] are default to 0011.
2, PWD = Power-Up Default
The ICS9248-195 is the single chip clock solution for Notebook designs using the 440BX, MX, VIA PM/PL/PLE 133
style chip set, with Coppermine or Tualatin processor, for Note book applications. It provides all necessary clock signals
for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-
195 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
General Description
Bit
PWD
FS3
Bit2
FS2
Bit6
FS1
Bit5
FS0
Bit4
CPUCLK
PCICLK
Center
Spread %
Down
Spread%
0
0
0
0
66.67
33.33
0.35%
-0.70%
0
0
0
1
100.00
33.33
0.35%
-0.70%
0
0
1
0
66.67
33.33
0.60%
-1.20%
0
0
1
1
133.33
33.33
0.35%
-0.70%
0
1
0
0
66.67
33.33
0.23%
-0.45%
0
1
0
1
100.00
33.33
0.23%
-0.45%
0
1
1
0
100.00
33.33
0.60%
-1.20%
0
1
1
1
133.33
33.33
0.23%
-0.45%
1
0
0
0
66.67
33.33
0.45%
-0.90%
1
0
0
1
100.00
33.33
0.45%
-0.90%
1
0
1
0
90.00
30.00
0.35%
-0.70%
1
0
1
1
133.33
33.33
0.45%
-0.90%
1
1
0
0
70.00
35.00
0.35%
-0.70%
1
1
0
1
105.00
35.00
0.35%
-0.70%
1
1
1
0
133.33
33.33
0.60%
-1.20%
1
1
1
1
140.00
35.00
0.35%
-0.70%
0 - Normal
Note1
0011
Description
1
0
1
0 = Center Spread Spectrum Modulation
1 = Down Spread Spectrum Modulation
0 - Frequency is selected by hardware select pins. Latched inputs.
1 - Frequency is controlled by I
2
C programming.
0 - Running
1 - Tristate all outputs
0
1 - Spread Spectrum Enabled
Bit 0
Bit 7
Bit 3
Bit 2,
6:4
Bit 1
4
ICS9248-195
0375D--02/02/04
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched register values will be inverted from pin values. Default latch condition is for all latched inputs to
be floating (pulled up via internal resistor) at power-up.
Byte 2: Active/Inactive Register (1 = enable, 0 = disable)
t
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B
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0
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C
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P
Byte 1: Active/Inactive Register (1 = enable, 0 = disable)
Byte 3: Active/Inactive Register (1 = enable, 0 = disable)
t
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A
R
D
S
5
ICS9248-195
0375D--02/02/04
Byte 4: Active/Inactive Register (1 = enable, 0 = disable)
Byte 5: Active/Inactive Register (1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched register values will be inverted from pin values. Default latch condition is for all latched inputs to be floating
(pulled up via internal resistor) at power-up.
t
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5
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B
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8
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