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Integrated
Circuit
Systems, Inc.
ICS9250-28
Third party brands and names are the property of their respective owners.
Block Diagram
9250-28 Rev B 10/26/00
Recommended Application:
810/810E and 815 type chipset.
Output Features:
2 CPU (2.5V) (up to 133MHz achievable through I
2
C)
13 SDRAM (3.3V) (up to 133MHz achievable
through I
2
C)
2 PCI (3.3 V) @33.3MHz
1 IOAPIC (2.5V) @ 33.3 MHz
3 Hublink clocks (3.3 V) @ 66.6 MHz
2 (3.3V) @ 48 MHz (Non spread spectrum)
1 REF (3.3V) @ 14.318 MHz
Features:
Supports spread spectrum modulation,
0 to -0.5% down spread.
I
2
C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Alternate frequency selections available through I
2
C
control.
Functionality
Pin Configuration
56-Pin 300mil SSOP
* This input has a 50K
W pull-down to GND.
IOAPIC
VDDL
GND
*FS1/REF0
VDDREF
X1
X2
GND
VDD3V66
3V66_0
3V66_1
3V66_2
GND
VDDPCI
PCICLK0
PCICLK1
GND
FS0
GND
VDDA
PD#
SCLK
SDATA
GND
VDD48
48MHz_0
48MHz_1
FS2
VDDL
GND
CPUCLK0
CPUCLK1
GND
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
SDRAM4
VDDSDR
GND
SDRAM5
SDRAM6
VDDSDR
GND
SDRAM7
SDRAM8
SDRAM9
VDDSDR
GND
SDRAM10
SDRAM11
VDDSDR
GND
SDRAM12
ICS9250-28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Frequency Generator & Integrated Buffers for Celeron & P
II
/
III
TM
2
S
F
0
S
F
1
S
F
n
o
i
t
c
n
u
F
0
0
X
e
t
a
t
s
i
r
T
0
1
X
t
s
e
T
1
0
0
z
H
M
6
6
=
U
P
C
e
v
i
t
c
A
z
H
M
0
0
1
=
M
A
R
D
S
1
1
0
z
H
M
0
0
1
=
U
P
C
e
v
i
t
c
A
z
H
M
0
0
1
=
M
A
R
D
S
1
0
1
z
H
M
3
3
1
=
U
P
C
e
v
i
t
c
A
z
H
M
3
3
1
=
M
A
R
D
S
1
1
1
z
H
M
3
3
1
=
U
P
C
e
v
i
t
c
A
z
H
M
0
0
1
=
M
A
R
D
S
REF0
CPU66/100/133 [1:0]
3V66 (2:0)
SDRAM (12:0)
PCICLK (1:0)
IOAPIC
PLL2
48MHz (1:0)
X1
X2
XTAL
OSC
Control
Logic
Config
Reg
FS(2:0)
PD#
2
2
3
13
2
/2
/2
/3
/2
PLL1
Spread
Spectrum
SDATA
SCLK
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Power Groups
Analog
VDDREF = X1, X2
VDDA = PLL1
VDD48 = PLL2
Digital
VDD3V66, VDDPCI
VDDSDR, VDDL
2
ICS9250-28
The ICS9250-28 is part of a two chip clock solution for 810/810E and 815 type chipset. Combined with the
ICS9112-17, the ICS9250-28 provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces EMI by 8dB to 10
dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The
ICS9250-28 employs a proprietary closed loop design, which tightly controls the percentage of spreading over
process and temperature variations.
General Description
Pin Configuration
R
E
B
M
U
N
N
I
P
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M
A
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N
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P
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P
Y
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2
6
5
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2
L
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1
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4
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4
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3
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3
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1
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#
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3
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5
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7
4
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6
4
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4
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A
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0
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2
1
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n
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3
.
3
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h
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t
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1
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t
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V
5
.
2
.
s
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p
)
0
:
2
(
S
F
n
o
3
ICS9250-28
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
Clock Enable Configuration
#
D
P
K
L
C
U
P
C
M
A
R
D
S
C
I
P
A
O
I
z
H
M
6
6
K
L
C
I
C
P
,
F
E
R
z
H
M
8
4
c
s
O
s
O
C
V
0
W
O
L
W
O
L
W
O
L
W
O
L
W
O
L
W
O
L
F
F
O
F
F
O
1
N
O
N
O
N
O
N
O
N
O
N
O
N
O
N
O
5
1
8
n
o
i
t
i
d
n
o
C
n
o
i
t
p
m
u
s
n
o
c
y
l
p
p
u
s
V
5
.
2
x
a
M
,
s
d
a
o
l
p
a
c
e
t
e
r
c
s
i
d
x
a
M
V
5
2
6
.
2
=
2
q
d
d
V
D
N
G
r
o
3
q
d
d
V
=
s
t
u
p
n
i
c
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t
a
t
s
l
l
A
n
o
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t
p
m
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p
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5
.
2
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a
M
,
s
d
a
o
l
p
a
c
e
t
e
r
c
s
i
d
x
a
M
V
5
6
4
.
3
=
2
q
d
d
V
D
N
G
r
o
3
q
d
d
V
=
s
t
u
p
n
i
c
i
t
a
t
s
l
l
A
e
d
o
M
n
w
o
d
r
e
w
o
P
0
=
#
N
W
D
R
W
P
(
A
m
0
1
A
m
0
1
z
H
M
6
6
e
v
i
t
c
A
l
l
u
F
0
1
0
=
]
0
:
2
[
S
F
A
m
0
7
A
m
0
0
4
z
H
M
0
0
1
e
v
i
t
c
A
l
l
u
F
1
1
0
=
]
0
:
2
[
S
F
A
m
0
0
1
A
m
0
0
4
z
H
M
3
3
1
e
v
i
t
c
A
l
l
u
F
1
1
1
=
]
0
:
2
[
S
F
A
m
0
3
1
A
m
0
5
4
4
ICS9250-28
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
2
S
F
0
S
F
1
S
F
U
P
C
M
A
R
D
S
6
6
V
3
I
C
P
z
H
M
8
4
F
E
R
C
I
P
A
O
I
0
0
X
e
t
a
t
s
i
r
T
e
t
a
t
s
i
r
T
e
t
a
t
s
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r
T
e
t
a
t
s
i
r
T
e
t
a
t
s
i
r
T
e
t
a
t
s
i
r
T
e
t
a
t
s
i
r
T
0
1
X
2
/
K
L
C
T
2
/
K
L
C
T
3
/
K
L
C
T
6
/
K
L
C
T
2
/
K
L
C
T
K
L
C
T
6
/
K
L
C
T
1
0
0
z
H
M
6
.
6
6
z
H
M
0
0
1
z
H
M
6
.
6
6
z
H
M
3
.
3
3
z
H
M
8
4
z
H
M
8
1
3
.
4
1
z
H
M
3
.
3
3
1
1
0
z
H
M
0
0
1
z
H
M
0
0
1
z
H
M
6
.
6
6
z
H
M
3
.
3
3
z
H
M
8
4
z
H
M
8
1
3
.
4
1
z
H
M
3
.
3
3
1
0
1
z
H
M
3
3
1
z
H
M
3
3
1
z
H
M
6
.
6
6
z
H
M
3
.
3
3
z
H
M
8
4
z
H
M
8
1
3
.
4
1
z
H
M
3
.
3
3
1
1
1
z
H
M
3
3
1
z
H
M
0
0
1
z
H
M
6
.
6
6
z
H
M
3
.
3
3
z
H
M
8
4
z
H
M
8
1
3
.
4
1
z
H
M
3
.
3
3
Truth Table
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always
with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the
default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the
CPU is at the 133MHz FSB speed as shown in this table. The CPU, 3V66, PCI, and IOAPIC clocks will be glitch
free during this transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "0".
Note3: Undefined bits can be written either as "1 or 0"
t
i
B
n
o
i
t
p
i
t
c
s
e
D
D
W
P
7
t
i
B
)
2
e
t
o
N
(
t
i
b
d
e
v
r
e
s
e
R
S
C
I
0
6
t
i
B
)
2
e
t
o
N
(
t
i
b
d
e
v
r
e
s
e
R
S
C
I
0
5
t
i
B
)
2
e
t
o
N
(
t
i
b
d
e
v
r
e
s
e
R
S
C
I
0
4
t
i
B
)
2
e
t
o
N
(
t
i
b
d
e
v
r
e
s
e
R
S
C
I
0
3
t
i
B
)
2
e
t
o
N
(
t
i
b
d
e
v
r
e
s
e
R
S
C
I
0
2
t
i
B
)
3
e
t
o
N
(
t
i
b
d
e
n
i
f
e
d
n
U
X
1
t
i
B
)
3
e
t
o
N
(
t
i
b
d
e
n
i
f
e
d
n
U
X
0
t
i
B
0
t
i
B
0
S
F
1
S
F
K
L
C
U
P
C
z
H
M
M
A
R
D
S
z
H
M
6
6
V
3
z
H
M
K
L
C
I
C
P
z
H
M
C
I
P
A
O
I
z
H
M
0
1
e
t
o
N
0
0
0
6
6
.
6
6
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
0
1
0
0
.
0
0
1
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
0
0
1
2
3
.
3
3
1
2
3
.
3
3
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
0
1
1
2
3
.
3
3
1
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
1
0
0
6
6
.
6
6
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
1
1
0
0
.
0
0
1
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
1
0
1
2
3
.
3
3
1
2
3
.
3
3
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
1
1
1
2
3
.
3
3
1
2
3
.
3
3
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
5
ICS9250-28
Byte 0: Control Register
(1 = enable, 0 = disable)
Byte 1: Control Register
(1 = enable, 0 = disable)
t
i
B
#
n
i
P
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
-
D
I
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
6
t
i
B
-
D
I
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
t
i
B
-
D
I
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
t
i
B
-
D
I
d
e
v
r
e
s
e
R
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
3
t
i
B
-
m
u
r
t
c
e
p
S
d
a
e
r
p
S
)
f
f
O
=
0
/
n
O
=
1
(
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
2
t
i
B
7
2
1
z
H
M
8
4
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
t
i
B
6
2
0
z
H
M
8
4
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
t
i
B
-
D
I
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
t
i
B
#
n
i
P
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
8
3
7
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
6
t
i
B
1
4
6
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
t
i
B
2
4
5
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
t
i
B
5
4
4
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
3
t
i
B
6
4
3
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
2
t
i
B
7
4
2
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
t
i
B
0
5
1
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
t
i
B
1
5
0
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
Note: Reserved ID bits must be written as "0"
Byte 2: Control Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bit can be wirtten with either a "1" or "0".
t
i
B
#
n
i
P
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
2
1
)
P
G
A
(
2
-
6
6
V
3
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
6
t
i
B
9
2
2
1
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
t
i
B
2
3
1
1
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
t
i
B
3
3
0
1
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
3
t
i
B
6
3
9
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
2
t
i
B
7
3
8
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
t
i
B
6
1
1
K
L
C
I
C
P
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
t
i
B
-
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
6
ICS9250-28
Group Timing Relationship Table
1
Byte 4: Reserved Register
(1 = enable, 0 = disable)
t
i
B
#
n
i
P
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
-
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
6
t
i
B
-
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
t
i
B
-
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
t
i
B
-
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
3
t
i
B
-
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
2
t
i
B
-
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
t
i
B
-
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
t
i
B
-
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
p
u
o
r
G
z
H
M
6
6
U
P
C
z
H
M
0
0
1
M
A
R
D
S
z
H
M
0
0
1
U
P
C
z
H
M
0
0
1
M
A
R
D
S
z
H
M
3
3
1
U
P
C
z
H
M
0
0
1
M
A
R
D
S
z
H
M
3
3
1
U
P
C
z
H
M
3
3
1
M
A
R
D
S
t
e
s
f
f
O
e
c
n
a
r
e
l
o
T
t
e
s
f
f
O
e
c
n
a
r
e
l
o
T
t
e
s
f
f
O
e
c
n
a
r
e
l
o
T
t
e
s
f
f
O
e
c
n
a
r
e
l
o
T
M
A
R
D
S
o
t
U
P
C
s
n
5
.
2
-
s
p
0
0
5
s
n
0
.
5
s
p
0
0
5
s
n
0
.
0
s
p
0
0
5
s
n
5
7
.
3
s
p
0
0
5
6
6
V
3
o
t
U
P
C
s
n
5
.
7
s
p
0
0
5
s
n
0
.
5
s
p
0
0
5
s
n
0
.
0
s
p
0
0
5
s
n
0
.
0
s
p
0
0
5
6
6
V
3
o
t
M
A
R
D
S
s
n
0
.
0
s
p
0
0
5
s
n
0
.
0
s
p
0
0
5
s
n
0
.
0
s
p
0
0
5
s
n
5
7
.
3
-
s
p
0
0
5
I
C
P
o
t
6
6
V
3
s
n
5
.
3
-
5
.
1
s
p
0
0
5
s
n
5
.
3
-
5
.
1
s
p
0
0
5
s
n
5
.
3
-
5
.
1
s
p
0
0
5
s
n
5
.
3
-
5
.
1
s
p
0
0
5
I
C
P
o
t
I
C
P
s
n
0
.
0
s
p
0
0
5
s
n
0
.
0
s
p
0
0
5
s
p
0
0
5
s
n
0
.
1
s
n
0
.
0
s
p
0
0
5
T
O
D
&
B
S
U
h
c
n
y
s
A
A
/
N
h
c
n
y
s
A
A
/
N
h
c
n
y
s
A
A
/
N
h
c
n
y
s
A
A
/
N
7
ICS9250-28
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C
Maximum Case Operating Temperature . . . . . . +135C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+0.3
V
Input Low Voltage
V
IL
V
SS
-0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
-5
5
A
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
-5
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
C
L
= 0 pF; @ 66/100 MHz
138
200
C
L
= 0 pF; @ 100/100 MHz
126
200
C
L
= 0 pF; @ 133/133 MHz
172
200
C
L
= 0 pF; @ 133/100 MHz
141
200
C
L
= Max loads; @ 66/100 MHz
339
400
C
L
= Max loads; @ 100/100 MHz
328
400
C
L
= Max loads; @ 133/133 MHz
383
450
C
L
= Max loads; @ 133/100 MHz
340
400
C
L
= 0 pF; @ 66/100 MHz
9
15
C
L
= 0 pF; @ 100/100 MHz
11
18
C
L
= 0 pF; @ 133/133 MHz
13
20
C
L
= 0 pF; @ 133/100 MHz
13
20
C
L
= Max loads; @ 66/100 MHz
13
35
C
L
= Max loads; @ 100/100 MHz
23
60
C
L
= Max loads; @ 133/133 MHz
29
60
C
L
= Max loads; @ 133/100 MHz
30
60
I
DD3.3PD
C
L
= Max loads
251
400
I
DD.25PD
Input address VDD or GND
<1
10
Input Frequency
F
i
V
DD
= 3.3 V
12
14.318
16
MHz
Transition time
1
T
trans
To 1st crossing of target frequency
3
ms
Settling time
1
T
s
From 1st crossing to 1% target frequency
3
ms
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target frequency
3
ms
t
PZH
,t
PZL
Output enable delay (all outputs)
1
10
ns
t
PHZ
,t
PLZ
Output disable delay (all outputs)
1
10
ns
1
Guaranteed by design, not 100% tested in production.
Delay
1
mA
mA
I
DD2.5OP
A
Powerdown Current
Operating Supply
Current
Input Low Current
A
mA
mA
I
DD3.3OP
8
ICS9250-28
Electrical Characteristics - CPU
T
A
= 0 - 70C; V
DDL
= 2.5 V +/-5%; C
L
= 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
R
DSP2B
1
V
O
= V
DD
*(0.5)
13.5
16
45
Output Impedance
R
DSN2B
1
V
O
= V
DD
*(0.5)
13.5
21
45
Output High Voltage
V
OH2B
I
OH
= -1 mA
2
V
Output Low Voltage
V
OL2B
I
OL
= 1 mA
0.4
V
V
OH @ MIN
= 1.0 V
-27
-68
V
OH @ MAX
= 2.375 V
-9
-27
V
OL @ MIN
= 1.2 V
27
54
V
OL @ MAX
= 0.3 V
11
30
Rise Time
1
t
r2B
V
OL
= 0.4 V, V
OH
= 2.0 V
0.4
1.1
1.6
ns
Fall Time
1
t
f2B
V
OH
= 2.0 V, V
OL
= 0.4 V
0.4
1.1
1.6
ns
Duty Cycle
1
d
t2B
V
T
= 1.25 V
45
49
55
%
Skew window
1
t
sk2B
V
T
= 1.25 V
45
175
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
V
T
= 1.25 V
135
250
ps
1
Guaranteed by design, not 100% tested in production.
mA
mA
Output High Current
Output Low Current
I
OH2B
I
OL2B
Electrical Characteristics - 3V66
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
R
DSP1B
1
V
O
= V
DD
*(0.5)
12
14
55
Output Impedance
R
DSN1B
1
V
O
= V
DD
*(0.5)
12
14.5
55
Output High Voltage
V
OH1
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= 1 mA
0.55
V
V
OH @ MIN
= 1.0 V
-33
-108
V
OH @ MAX
= 3.135 V
-9
-33
V
OL @ MIN
= 1.95 V
30
95
V
OL @ MAX
= 0.4 V
29
38
Rise Time
1
t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V
0.4
1.2
1.6
ns
Fall Time
1
t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V
0.4
1.2
1.6
ns
Duty Cycle
1
d
t1
V
T
= 1.5 V
45
49
55
%
Skew window
1
t
sk1
V
T
= 1.5 V
135
175
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc1
V
T
= 1.5 V
175
500
ps
1
Guaranteed by design, not 100% tested in production.
Output High Current
Output Low Current
mA
mA
I
OH1
I
OL1
9
ICS9250-28
Electrical Characteristics - IOAPIC
T
A
= 0 - 70C; V
DDL
= 2.5 V +/-5%; C
L
= 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
R
DSP4B
1
V
O
= V
DD
*(0.5)
9
16
30
Output Impedance
R
DSN4B
1
V
O
= V
DD
*(0.5)
9
20
30
Output High Voltage
V
OH4B
I
OH
= -1 mA
2
V
Output Low Voltage
V
OL4B
I
OL
= 1 mA
0.4
V
V
OH @ MIN
= 1.0 V
-27
-68
V
OH @ MAX
= 2.375 V
-9
-27
V
OL @ MIN
= 1.2 V
27
54
V
OL @ MAX
= 0.3 V
11
30
Rise Time
1
t
r4B
V
OL
= 0.4 V, V
OH
= 2.0 V
0.4
1.1
1.6
ns
Fall Time
1
t
f4B
V
OH
= 2.0 V, V
OL
= 0.4 V
0.4
1.1
1.6
ns
Duty Cycle
1
d
t4B
V
T
= 1.25 V
45
49
55
%
Jitter, Cycle-to-cycle
1
t
jcyc-cyc4B
V
T
= 1.25 V
180
500
ps
1
Guaranteed by design, not 100% tested in production.
Output High Current
I
OH4B
mA
Output Low Current
I
OL4B
mA
Electrical Characteristics - SDRAM
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 20-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
R
DSP3B
1
V
O
= V
DD
*(0.5)
10
12
24
Output Impedance
R
DSN3B
1
V
O
= V
DD
*(0.5)
10
15
24
Output High Voltage
V
OH3
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL3
I
OL
= 1 mA
0.4
V
V
OH @ MIN
= 2.0 V
-54
-92
V
OH @ MAX
= 3.135 V
-16
-46
V
OL @ MIN
= 1.0 V
54
68
V
OL @ MAX
= 0.4 V
29
53
Rise Time
1
t
r3
V
OL
= 0.4 V, V
OH
= 2.4 V
0.4
1
1.6
ns
Fall Time
1
t
f3
V
OH
= 2.4 V, V
OL
= 0.4 V
0.4
1.5
1.6
ns
Duty Cycle
1
d
t3
V
T
= 1.5 V
45
52
55
%
Skew window
1
t
sk3
V
T
= 1.5 V
120
250
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc3
V
T
= 1.5 V
135
250
ps
1
Guaranteed by design, not 100% tested in production.
mA
mA
Output High Current
Output Low Current
I
OH3
I
OL3
10
ICS9250-28
Electrical Characteristics - PCI
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
R
DSP1B
1
V
O
= V
DD
*(0.5)
12
15
55
Output Impedance
R
DSN1B
1
V
O
= V
DD
*(0.5)
12
15
55
Output High Voltage
V
OH1
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= 1 mA
0.55
V
V
OH @ MIN
= 1.0 V
-33
-106
V
OH @ MAX
= 3.135 V
-14
-33
V
OL @ MIN
= 1.95 V
30
94
V
OL @ MAX
= 0.4 V
29
38
Rise Time
1
t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V
0.4
1.3
2
ns
Fall Time
1
t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V
0.4
1.4
2
ns
Duty Cycle
1
d
t1
V
T
= 1.5 V
45
51
55
%
Skew window
1
t
sk1
V
T
= 1.5 V
20
500
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc1
V
T
= 1.5 V
175
500
ps
1
Guaranteed by design, not 100% tested in production.
Output High Current
I
OH1
mA
Output Low Current
I
OL1
mA
Electrical Characteristics - REF, 48MHz_0 (Pin 26)
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
R
DSP5B
1
V
O
= V
DD
*(0.5)
20
29
60
Output Impedance
R
DSN5B
1
V
O
= V
DD
*(0.5)
20
27
60
Output High Voltage
V
OH15
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL5
I
OL
= 1 mA
0.55
V
V
OH @ MIN
= 1.0 V
-29
-54
V
OH @ MAX
= 3.135 V
-11
-23
V
OL @ MIN
= 1.95 V
29
54
V
OL @ MAX
= 0.4 V
16
27
Rise Time
1
t
r5
V
OL
= 0.4 V, V
OH
= 2.4 V
0.4
1.3
4
ns
Fall Time
1
t
f5
V
OH
= 2.4 V, V
OL
= 0.4 V
0.4
1.6
4
ns
Duty Cycle
1
d
t5
V
T
= 1.5 V
45
53
55
%
Jitter, Cycle-to-cycle
1
t
jcyc-cyc5
V
T
= 1.5 V, Fixed clocks
160
500
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc5
V
T
= 1.5 V, Ref clocks
420
1000
ps
1
Guaranteed by design, not 100% tested in production.
Output High Current
I
OH5
mA
Output Low Current
I
OL5
mA
11
ICS9250-28
Electrical Characteristics - 48MHz_1 (Pin 27)
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10-15 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
R
DSP3B
1
V
O
= V
DD
*(0.5)
10
15
24
Output Impedance
R
DSN3B
1
V
O
= V
DD
*(0.5)
10
15
24
Output High Voltage
V
OH3
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL3
I
OL
= 1 mA
0.55
V
V
OH @ MIN
= 2.0 V
-54
-82
V
OH @ MAX
= 3.135 V
-20
-46
V
OL @ MIN
= 1.0 V
54
95
V
OL @ MAX
= 0.4 V
28
53
Rise Time
1
t
r3
V
OL
= 0.4 V, V
OH
= 2.4 V
0.4
1.1
1.6
ns
Fall Time
1
t
f3
V
OH
= 2.4 V, V
OL
= 0.4 V
0.4
1.3
1.6
ns
Duty Cycle
1
d
t3
V
T
= 1.5 V
45
53
55
%
Jitter, Cycle-to-cycle
1
t
jcyc-cyc3B
V
T
= 1.5 V
145
500
ps
1
Guaranteed by design, not 100% tested in production.
Output High Current
I
OH3
mA
Output Low Current
I
OL3
mA
12
ICS9250-28
Group Skews (CPU 66 MHz, SDRAM 100MHz)
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
Refer to Group Offset Waveforms diagram for definition of transition edges.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CPU to SDRAM Skew
1
T
sk1 CPU-SDRAM
-3
-2.7
-2
ns
Skew Window
1
T
w1 CPU-SDRAM
0
165
500
ps
CPU to 3V66 Skew
1
T
sk1 CPU-3V66
7
7.6
8
ns
Skew Window
1
T
w1 CPU-3V66
0
105
500
ps
SDRAM to 3V66 Skew
1
T
sk1 SDRAM-3V66
-500
180
500
ps
Skew Window
1
T
w1 SDRAM-3V66
0
210
500
ps
3V66 to PCI Skew
1
T
sk1 3V66-PCI
1.5
2.1
3.5
ns
Skew Window
1
T
w1 3V66-PCI
0
90
500
ps
IOAPIC to PCI Skew
1
T
sk1 IOAPIC-PCI
-1
-0.1
1
ns
Skew Window
1
T
w1 IOAPIC-PCI
0
0
1
ns
1
Guaranteed by design, not 100% tested in production.
Group Skews (CPU 100 MHz, SDRAM 100MHz)
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
Refer to Group Offset Waveforms diagram for definition of transition edges.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CPU to SDRAM Skew
1
T
sk2 CPU-SDRAM
4.5
4.9
5.5
ns
Skew Window
1
T
w2 CPU-SDRAM
0
180
500
ps
CPU to 3V66 Skew
1
T
sk2 CPU-3V66
4.5
5
5.5
ns
Skew Window
1
T
w2 CPU-3V66
0
100
500
ps
SDRAM to 3V66 Skew
1
T
sk2 SDRAM-3V66
-500
175
500
ps
Skew Window
1
T
w2 SDRAM-3V66
0
200
500
ps
3V66 to PCI Skew
1
T
sk2 3V66-PCI
1.5
2.1
3.5
ns
Skew Window
1
T
w2 3V66-PCI
0
90
500
ps
IOAPIC to PCI Skew
1
T
sk2 IOAPIC-PCI
-1
-0.1
1
ns
Skew Window
1
T
w2 IOAPIC-PCI
0
0
1
ns
1
Guaranteed by design, not 100% tested in production.
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM, 3V66 @ 1.5 V
3V66, PCI @ 1.5 V
IOAPIC @ 1.25 V, PCI @ 1.5 V
CPU @ 1.25 V, SDRAM @ 1.5 V
CPU @ 1.25 V, SDRAM @ 1.5 V
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM, 3V66 @ 1.5 V
3V66, PCI @ 1.5 V
IOAPIC @ 1.25 V, PCI @ 1.5 V
13
ICS9250-28
Group Skews (CPU 133 MHz, SDRAM 133MHz)
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
Refer to Group Offset Waveforms diagram for definition of transition edges.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CPU to SDRAM Skew
1
T
sk3 CPU-SDRAM
3.25
3.45
4.25
ns
Skew Window
1
T
w3 CPU-SDRAM
0
155
500
ps
CPU to 3V66 Skew
1
T
sk3 CPU-3V66
-500
120
500
ps
Skew Window
1
T
w3 CPU-3V66
0
120
500
ps
SDRAM to 3V66 Skew
1
T
sk3 SDRAM-3V66
-3.25
-3.08
-4.25
ps
Skew Window
1
T
w3 SDRAM-3V66
0
175
500
ps
3V66 to PCI Skew
1
T
sk3 3V66-PCI
1.5
2.2
3.5
ns
Skew Window
1
T
w3 3V66-PCI
0
80
500
ps
IOAPIC to PCI Skew
1
T
sk3 IOAPIC-PCI
-1
-0.1
1
ns
Skew Window
1
T
w3 IOAPIC-PCI
0
0
1
ns
1
Guaranteed by design, not 100% tested in production.
Group Skews (CPU133 MHz, SDRAM 100MHz)
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
Refer to Group Offset Waveforms diagram for definition of transition edges.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CPU to SDRAM Skew
1
T
sk3 CPU-SDRAM
CPU @ 1.25 V, SDRAM @ 1.5 V
-500
-15
500
ps
Skew Window
1
T
w3 CPU-SDRAM
0
165
500
ps
CPU to 3V66 Skew
1
T
sk3 CPU-3V66
CPU @ 1.25 V, 3V66 @ 1.5 V
-500
165
500
ps
Skew Window
1
T
w3 CPU-3V66
0
105
500
ps
SDRAM to 3V66 Skew
1
T
sk3 SDRAM-3V66
SDRAM, 3V66 @ 1.5 V
-500
185
500
ps
Skew Window
1
T
w3 SDRAM-3V66
0
185
500
ps
3V66 to PCI Skew
1
T
sk3 3V66-PCI
3V66, PCI @ 1.5 V
1.5
2.2
3.5
ns
Skew Window
1
T
w3 3V66-PCI
0
60
500
ps
IOAPIC to PCI Skew
1
T
sk3 IOAPIC-PCI
IOAPIC @ 1.25 V, PCI @ 1.5 V
-1
-0.1
1
ns
Skew Window
1
T
w3 IOAPIC-PCI
0
0
1
ns
1
Guaranteed by design, not 100% tested in production.
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM, 3V66 @ 1.5 V
3V66, PCI @ 1.5 V
IOAPIC @ 1.25 V, PCI @ 1.5 V
CPU @ 1.25 V, SDRAM @ 1.5 V
14
ICS9250-28
Group Offset Waveforms
Cycle Repeats
0ns
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 133MHz
SDRAM 100MHz
3V66MHz
PCI 33MHz
APIC 33MHz
REF 14.318MHz
USB 48MHz
10ns
20ns
30ns
40ns
15
ICS9250-28
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Write:
16
ICS9250-28
Connections to VDD:
General Layout Precautions:
1) Use a ground plane on the top routing
layer of the PCB in all areas not used
by traces.
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
Notes:
1 All clock outputs should have
provisions for a 15pf capacitor
between the clock output and series
terminating resistor. Not shown in
all places to improve readability of
diagram.
2 Optional crystal load capacitors are
recommended. They should be
included in the layout but not
inserted unless needed.
Component Values:
C1 : Crystal load values determined by user
C2 : 22F/20V/D case/Tantalum
AVX TAJD226M020R
C3 : 15pF capacitor
FB = Fair-Rite products 2512066017X1
All unmarked capacitors are 0.01F ceramic
3.3V Power Route
Ground
2.5V Power Route
C1
C1
2
C3
1
Clock Load
Ferrite
Bead
VDD
C2
22F/20V
Tantalum
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
Ferrite
Bead
VDD
C2
22F/20V
Tantalum
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
17
ICS9250-28
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Ordering Information
ICS9250yF-28-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP - T
MIN
MAX
MIN
MAX
A
2.413
2.794
.095
.110
A1
0.203
0.406
.008
.016
b
0.203
0.343
.008
.0135
c
0.127
0.254
.005
.010
D
E
10.033
10.668
.395
.420
E1
7.391
7.595
.291
.299
e
0.635 BASIC
0.025 BASIC
h
0.381
0.635
.015
.025
L
0.508
1.016
.020
.040
N
0
8
0
8
VARIATIONS
MIN
MAX
MIN
MAX
28
9.398
9.652
.370
.380
34
11.303
11.557
.445
.455
48
15.748
16.002
.620
.630
56
18.288
18.542
.720
.730
64
20.828
21.082
.820
.830
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
SEE VARIATIONS
N
D mm.
D (inch)
SEE VARIATIONS
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