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Электронный компонент: ICS9250-29

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Integrated
Circuit
Systems, Inc.
ICS9250-29
Third party brands and names are the property of their respective owners.
Block Diagram
9250-29 Rev A 02/01/01
Recommended Application:
Solano type chipset.
Output Features:
2 CPU (2.5V) (up to 133MHz achievable through I
2
C)
13 SDRAM (3.3V) (up to 133MHz achievable
through I
2
C)
5 PCI (3.3 V) @33.3MHz
1 IOAPIC (2.5V) @ 33.3 MHz
3 Hublink clocks (3.3 V) @ 66.6 MHz
2 (3.3V) @ 48 MHz (Non spread spectrum)
1 REF (3.3V) @ 14.318 MHz
Features:
Supports spread spectrum modulation,
0 to -0.5% down spread.
I
2
C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Alternate frequency selections available through I
2
C
control.
Functionality
Pin Configuration
56-Pin 300mil SSOP
* This input has a 50K
9 pull-down to GND.
** This input has a 50K
9pull-up to VDD
IOAPIC
VDDL
GNDL
*FS1/REF
VDDR
X1
X2
GNDR
VDD3
3V66-0
3V66-1
3V66-2
GND3
PCICLK0
PCICLK1
PCICLK2
VDD2
GND2
PCICLK3
PCICLK4
FS0
GNDA
VDDA
SCLK
SDATA
GNDF
VDDF
48MHz_0
GNDL
VDDL
CPUCLK0
CPUCLK1
GND1
SDRAM0
SDRAM1
VDD1
GND1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDD1
GND1
SDRAM6
SDRAM7
SDRAM8
SDRAM9
VDD1
GND1
SDRAM10
SDRAM11
VDD1
GND1
SDRAM12
TRISTATE#/PD#**
48MHz_1
ICS9250-29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
REF
CPU66/100/133 [1:0]
VDDL
3V66 [2:0]
SDRAM [12:0]
PCICLK [4:0]
IOAPIC
VDDL
PLL2
48MHz [1:0]
X1
X2
XTAL
OSC
Control
Logic
Config
Reg
FS(1:0)
PD#
TRISTATE#
2
2
3
13
5
/2
/2
/3
/2
PLL1
Spread
Spectrum
SDATA
SCLK
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1
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
Power Groups
VDDA, GNDA = CPU, PLL (analog)
VDDF, GNDF = Fixed PLL, 48M (analog/digital)
VDDR, GNDR = REF, X1, X2 (analog/digital)
VDD3, GND3 = 3V66 (digital)
VDD2, GND2 = PCI (digital)
VDD1, GND1 = SDRAM (digital)
VDDL, GNDL = IOAPIC, CPU (digital)
background image
2
ICS9250-29
The ICS9250-29 is a single chip clock solution for Solano type chipset. It provides all necessary clock signals for such
a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-29
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
General Description
Pin Configuration
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background image
3
ICS9250-29
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the
output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
Clock Enable Configuration
#
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background image
4
ICS9250-29
1.
The ICS clock generator is a slave/receiver, I
2
C (SMB) component. It is only a "write" mode SMB device, no readback on
this part. Read-Back will lock up the PIIX-4 due to the Byte count of 00
H
.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The
data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
 Controller (host) sends a dummy command code
ICS clock will acknowledge
 Controller (host) sends a dummy byte count
ICS clock will acknowledge
 Controller (host) starts sending first byte (Byte 0) through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Write:
Note: This clock does not support Read Back. Doing a
read back will lock up the PIIX-4 system.
background image
5
ICS9250-29
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0
0
1
z
H
M
6
.
6
6
z
H
M
3
.
3
3
z
H
M
8
4
z
H
M
8
1
3
.
4
1
z
H
M
3
.
3
3
1
1
0
z
H
M
0
0
1
z
H
M
0
0
1
z
H
M
6
.
6
6
z
H
M
3
.
3
3
z
H
M
8
4
z
H
M
8
1
3
.
4
1
z
H
M
3
.
3
3
1
0
1
z
H
M
3
3
1
z
H
M
3
3
1
z
H
M
6
.
6
6
z
H
M
3
.
3
3
z
H
M
8
4
z
H
M
8
1
3
.
4
1
z
H
M
3
.
3
3
1
1
1
z
H
M
3
3
1
z
H
M
0
0
1
z
H
M
6
.
6
6
z
H
M
3
.
3
3
z
H
M
8
4
z
H
M
8
1
3
.
4
1
z
H
M
3
.
3
3
Truth Table
Byte 0: Control Register
(1 = enable, 0 = disable)
Byte 1: Control Register
(1 = enable, 0 = disable)
t
i
B
#
n
i
P
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
-
)
D
I
d
e
v
r
e
s
e
R
(
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
6
t
i
B
-
)
D
I
d
e
v
r
e
s
e
R
(
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
t
i
B
-
)
D
I
d
e
v
r
e
s
e
R
(
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
t
i
B
-
)
D
I
d
e
v
r
e
s
e
R
(
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
3
t
i
B
-
m
u
r
t
c
e
p
S
d
a
e
r
p
S
0
)
f
f
O
=
0
/
n
O
=
1
(
2
t
i
B
9
2
1
_
z
H
M
8
4
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
t
i
B
8
2
0
_
z
H
M
8
4
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
t
i
B
-
)
D
I
d
e
v
r
e
s
e
R
(
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
t
i
B
#
n
i
P
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
4
7
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
6
t
i
B
1
4
6
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
t
i
B
4
4
5
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
t
i
B
5
4
4
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
3
t
i
B
6
4
3
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
2
t
i
B
7
4
2
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
t
i
B
0
5
1
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
t
i
B
1
5
0
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
Note:
Reserved ID bits must be written with "0"