Integrated
Circuit
Systems, Inc.
ICS9250-51
Block Diagram
0405A--03/22/02
Recommended Application:
815 B-Step type chipset.
Output Features:
3 CPU (2.5V) (up to 133MHz achievable through
I
2
C)
9 SDRAM (3.3V) (up to 133MHz achievable
through I
2
C)
7 PCI (3.3 V) @33.3MHz
2 IOAPIC (2.5V) @ 33.3 MHz
3 Hublink clocks (3.3 V) @ 66.6 MHz
2 (3.3V) @ 48 MHz (Non spread spectrum)
1 REF (3.3V) @ 14.318 MHz
Features:
Supports spread spectrum modulation,
0 to -0.5% down spread.
I
2
C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Alternate frequency selections available through I
2
C
control.
815 B-Step compliant for frequency select latched
inputs. Internal power-on-reset and latching, are
delayed until Vtt_PWRGD signal is gated high onto
the PD#.
Functionality
Pin Configuration
56-Pin 300mil SSOP
* This input has a 50K
pull-down to GND.
*FS2//REF0
VDD
X1
X2
GND
GND
3V66-0
3V66-1
3V66-2
VDD
VDD
PCICLK_F
PCICLK0
GND
PCICLK1
PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
VDD
AVDD
AGND
GND
48MHz_0
48MHz_1
VDD48
FS0
GNDL
IOAPIC0
IOAPIC1
VDDL
CPUCLK0
VDDL0
CPUCLK1
CPUCLK2
GNDL
GND
SDRAM0
SDRAM1
VDD
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD
SDRAM6
SDRAM7
GND
SDRAM_F
VDD
Vtt_PWRGD/PD#
SCLK
SDATA
FS1
ICS9250-51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Frequency Generator & Integrated Buffers for Celeron & P
II
/
III
TM
2
S
F
1
S
F
0
S
F
n
o
i
t
c
n
u
F
X
0
0
e
t
a
t
s
i
r
T
X
0
1
t
s
e
T
0
1
0
z
H
M
6
6
=
U
P
C
e
v
it
c
A
z
H
M
0
0
1
=
M
A
R
D
S
0
1
1
z
H
M
0
0
1
=
U
P
C
e
v
it
c
A
z
H
M
0
0
1
=
M
A
R
D
S
1
1
0
z
H
M
3
3
1
=
U
P
C
e
v
it
c
A
z
H
M
3
3
1
=
M
A
R
D
S
1
1
1
z
H
M
3
3
1
=
U
P
C
e
v
it
c
A
z
H
M
0
0
1
=
M
A
R
D
S
REF0
CPU66/100/133 (2:0)
VDDL
3V66 (2:0)
SDRAM (7:0)
PCICLK (5:0)
IOAPIC (1:0)
VDDL
SDRAM_F
PCICLK_F
PLL2
48MHz (1:0)
X1
X2
XTAL
OSC
Control
Logic
Config
Reg
FS (2:0)
PD#
Vtt_PWRGD
2
3
3
8
6
2
/2
/2
/3
/2
PLL1
Spread
Spectrum
SDATA
SCLK
Power Groups
AVDD = Pin 22 Analog power for PLL
AGND = Pin 23 Analog ground
VDD48 = Pin 27 Analog power for 48MHz PLL
GND48 = Pin 24 Analog ground for 48MHz PLL
2
ICS9250-51
The ICS9250-51 is a single chip clock solution for 815 B-Step type chipset. It provides all necessary clock
signals for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces EMI by 8dB
to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The
ICS9250-51 employs a proprietary closed loop design, which tightly controls the percentage of spreading over
process and temperature variations.
General Description
Pin Configuration
R
E
B
M
U
N
N
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A
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2
3
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1
5
L
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V
5
.
2
3
ICS9250-51
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs,
all the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
Clock Enable Configuration
#
D
P
K
L
C
U
P
C
M
A
R
D
S
C
I
P
A
O
I
z
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M
6
6
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L
C
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,
F
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R
z
H
M
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4
c
s
O
s
O
C
V
0
W
O
L
W
O
L
W
O
L
W
O
L
W
O
L
W
O
L
F
F
O
F
F
O
1
N
O
N
O
N
O
N
O
N
O
N
O
N
O
N
O
5
1
8
n
o
i
t
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d
n
o
C
n
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t
p
m
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l
p
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V
5
.
2
x
a
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,
s
d
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l
p
a
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c
s
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d
x
a
M
V
5
2
6
.
2
=
2
q
d
d
V
D
N
G
r
o
3
q
d
d
V
=
s
t
u
p
n
i
c
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a
t
s
ll
A
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5
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2
x
a
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d
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l
p
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t
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s
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d
x
a
M
V
5
6
4
.
3
=
2
q
d
d
V
D
N
G
r
o
3
q
d
d
V
=
s
t
u
p
n
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c
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t
a
t
s
ll
A
e
d
o
M
n
w
o
d
r
e
w
o
P
0
=
#
N
W
D
R
W
P
(
A
m
0
1
A
m
0
1
z
H
M
6
6
e
v
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t
c
A
l
l
u
F
0
1
0
=
]
0
:
2
[
S
F
A
m
0
7
A
m
0
8
2
z
H
M
0
0
1
e
v
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t
c
A
l
l
u
F
1
1
0
=
]
0
:
2
[
S
F
A
m
0
0
1
A
m
0
8
2
z
H
M
3
3
1
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v
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t
c
A
l
l
u
F
1
1
1
=
]
0
:
2
[
S
F
4
ICS9250-51
2
S
F
1
S
F
0
S
F
U
P
C
M
A
R
D
S
6
6
V
3
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C
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i
r
T
e
t
a
t
s
i
r
T
e
t
a
t
s
i
r
T
e
t
a
t
s
i
r
T
X
0
1
2
/
K
L
C
T
2
/
K
L
C
T
3
/
K
L
C
T
6
/
K
L
C
T
2
/
K
L
C
T
K
L
C
T
6
/
K
L
C
T
0
1
0
z
H
M
6
.
6
6
z
H
M
0
0
1
6
.
6
6
z
H
M
z
H
M
3
.
3
3
z
H
M
8
4
8
1
3
.
4
1
z
H
M
3
.
3
3
z
H
M
0
1
1
z
H
M
0
0
1
z
H
M
0
0
1
6
.
6
6
z
H
M
z
H
M
3
.
3
3
z
H
M
8
4
8
1
3
.
4
1
z
H
M
3
.
3
3
z
H
M
1
1
0
z
H
M
3
3
1
z
H
M
3
3
1
6
.
6
6
z
H
M
z
H
M
3
.
3
3
z
H
M
8
4
8
1
3
.
4
1
z
H
M
3
.
3
3
z
H
M
1
1
1
z
H
M
3
3
1
z
H
M
0
0
1
6
.
6
6
z
H
M
z
H
M
3
.
3
3
z
H
M
8
4
8
1
3
.
4
1
z
H
M
3
.
3
3
z
H
M
Truth Table
Byte 0: Control Register
(1 = enable, 0 = disable)
t
i
B
#
n
i
P
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
D
I
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
6
t
i
B
D
I
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
t
i
B
D
I
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
t
i
B
D
I
d
e
v
r
e
s
e
R
0
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
3
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
)
f
f
O
=
0
/
n
O
=
1
(
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
2
t
i
B
6
2
1
z
H
M
8
4
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
t
i
B
5
2
0
z
H
M
8
4
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
t
i
B
9
4
2
K
L
C
U
P
C
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
Note: Reserved ID bits must be wirtten as "0".
Byte 1: Control Register
(1 = enable, 0 = disable)
t
i
B
#
n
i
P
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
6
3
7
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
6
t
i
B
7
3
6
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
t
i
B
9
3
5
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
t
i
B
0
4
4
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
3
t
i
B
2
4
3
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
2
t
i
B
3
4
2
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
t
i
B
5
4
1
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
t
i
B
6
4
0
M
A
R
D
S
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
5
ICS9250-51
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed,
always with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written
from the default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only
change if the CPU is at the 133MHz FSB speed as shown in this table. The CPU, 3v66, PCI, and IOAPIC
clocks will be glitch free during this transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "O".
Note3: Undefined bits can be written either as "1 or 0"
t
i
B
n
o
i
t
p
i
t
c
s
e
D
D
W
P
7
t
i
B
)
2
e
t
o
N
(
t
i
b
d
e
v
r
e
s
e
R
S
C
I
0
6
t
i
B
)
2
e
t
o
N
(
t
i
b
d
e
v
r
e
s
e
R
S
C
I
0
5
t
i
B
)
2
e
t
o
N
(
t
i
b
d
e
v
r
e
s
e
R
S
C
I
0
4
t
i
B
)
2
e
t
o
N
(
t
i
b
d
e
v
r
e
s
e
R
S
C
I
0
3
t
i
B
)
2
e
t
o
N
(
t
i
b
d
e
v
r
e
s
e
R
S
C
I
0
2
t
i
B
)
3
e
t
o
N
(
t
i
b
d
e
n
i
f
e
d
n
U
X
1
t
i
B
)
3
e
t
o
N
(
t
i
b
d
e
n
i
f
e
d
n
U
X
0
t
i
B
0
t
i
B
0
S
F
1
S
F
K
L
C
U
P
C
z
H
M
M
A
R
D
S
z
H
M
6
6
V
3
z
H
M
K
L
C
I
C
P
z
H
M
C
I
P
A
O
I
z
H
M
0
1
e
t
o
N
0
0
0
6
6
.
6
6
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
0
1
0
0
.
0
0
1
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
0
0
1
2
3
.
3
3
1
2
3
.
3
3
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
0
1
1
2
3
.
3
3
1
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
1
0
0
6
6
.
6
6
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
1
1
0
0
.
0
0
1
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
1
0
1
2
3
.
3
3
1
2
3
.
3
3
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
1
1
1
2
3
.
3
3
1
2
3
.
3
3
1
6
6
.
6
6
3
3
.
3
3
3
3
.
3
3
Byte 2: Control Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bit can be wirtten with either a "1" or "0".
t
i
B
#
n
i
P
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
9
)
P
G
A
(
2
-
6
6
V
3
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
6
t
i
B
0
2
5
K
L
C
I
C
P
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
t
i
B
9
1
4
K
L
C
I
C
P
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
t
i
B
8
1
3
K
L
C
I
C
P
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
3
t
i
B
6
1
2
K
L
C
I
C
P
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
2
t
i
B
5
1
1
K
L
C
I
C
P
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
t
i
B
3
1
0
K
L
C
I
C
P
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
t
i
B
-
t
i
b
d
e
n
i
f
e
d
n
U
X
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
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