ICS9250-18
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
Frequency Generator & Integrated Buffers for Celeron & P
II
/
III
TM
9250-18 Rev B 9/23/99
Functionality
Pin Configuration
Recommended Application:
BX, Appollo Pro 133 type of chip set.
Output Features:
3 - CPUs @2.5V, up to 166MHz.
17 - SDRAM @ 3.3V, up to 166MHz.
7 - PCI @3.3V
2 - IOAPIC @ 2.5V
1 - 48MHz, @3.3V fixed.
1 - 24MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
Features:
Up to 166MHz frequency support
Support power management: CPU, PCI, stop and Power
down Mode form I
2
C programming.
Spread spectrum for EMI control ( 0.25% center spread)
Uses external 14.318MHz crystal
Key Specifications:
CPU CPU: <175ps
CPU PCI: 1 - 4ns
PCI PCI: <500ps
SDRAM - SDRAM: <250ps
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
** Internal Pull-down resistor of 240K to GND on indicated inputs.
1. This output is double strength.
VDDREF
*FS2/REF1
*PCI_STOP#/REF0
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
*FS3/PCICLK0
GND
VDDPCI
BUFFERIN
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
SDATA
SCLK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
VDDLIOAPIC
IOAPIC0
IOAPIC_F
GND
CPUCLK_F
CPUCLK1
VDDLCPU
CPUCLK2
GND
CPU_STOP#
SDRAM_F
VDDSDR
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM12
SDRAM13
VDD48
24MHz/FS0*
48MHz/FSI*
1
ICS9250-18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
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{
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2
Block Diagram
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3
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS9250-18
Third party brands and names are the property of their respective owners.
Pin Configuration
Notes:
1:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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3
ICS9250-18
Third party brands and names are the property of their respective owners.
General Description
The ICS9250-18 is the single chip clock solution for Desktop/designs using BX, Appollo Pro 133 type of chip sets. It provides
all necessary clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-18
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
E
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4
ICS9250-18
Third party brands and names are the property of their respective owners.
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Write:
5
ICS9250-18
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: PWD = Power-Up Default
Note 1. Default at Power-up will be for latched logic inputs to define frequency as
displayed by Bit 3.
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4
.
3
3
0
0
1
0
0
0
0
.
3
0
1
3
3
.
4
3
0
0
1
0
1
1
0
.
2
1
1
4
3
.
7
3
0
0
1
1
0
1
0
.
8
6
1
0
.
4
3
0
0
1
1
1
7
.
0
0
1
7
5
.
3
3
0
1
0
0
0
0
0
.
0
2
1
0
0
.
0
4
0
1
0
0
1
9
9
.
4
1
1
3
3
.
8
3
0
1
0
1
0
9
9
.
9
0
1
6
6
.
6
3
0
1
0
1
1
0
0
.
5
0
1
0
0
.
5
3
0
1
1
0
0
0
0
.
0
4
1
0
0
.
5
3
0
1
1
0
1
0
0
.
0
5
1
0
5
.
7
3
0
1
1
1
0
0
0
.
4
2
1
0
0
.
1
3
0
1
1
1
1
9
.
3
3
1
5
2
.
3
3
1
0
0
0
0
0
0
.
5
3
1
5
7
.
3
3
1
0
0
0
1
9
9
.
9
2
1
0
5
.
2
3
1
0
0
1
0
0
0
.
6
2
1
0
5
.
1
3
1
0
0
1
1
0
0
.
8
1
1
3
3
.
9
3
1
0
1
0
0
8
9
.
5
1
1
6
6
.
8
3
1
0
1
0
1
0
0
.
5
9
7
6
.
1
3
1
0
1
1
0
0
0
.
0
9
0
0
.
0
3
1
0
1
1
1
1
0
.
5
8
4
3
.
8
2
1
1
0
0
0
0
0
.
6
6
1
0
5
.
1
4
1
1
0
0
1
1
0
.
0
6
1
0
0
.
0
4
1
1
0
1
0
9
9
.
4
5
1
5
7
.
8
3
1
1
0
1
1
5
9
.
7
4
1
9
9
.
6
3
1
1
1
0
0
8
9
.
5
4
1
0
5
.
6
3
1
1
1
0
1
8
9
.
3
4
1
9
9
.
5
3
1
1
1
1
0
9
9
.
1
4
1
0
5
.
5
3
1
1
1
1
1
1
0
.
8
3
1
0
5
.
4
3
3
t
i
B
s
t
u
p
n
i
d
e
h
c
t
a
l
,
t
c
e
l
e
s
e
r
a
w
d
r
a
h
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
0
4
:
7
,
2
t
i
B
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
1
0
1
t
i
B
l
a
m
r
o
N
-
0
)
d
a
e
r
p
S
r
e
t
n
e
C
(
%
5
2
.
0
d
e
l
b
a
n
E
m
u
r
t
c
e
p
S
d
a
e
r
p
S
-
1
1
0
t
i
B
g
n
i
n
n
u
R
-
0
s
t
u
p
t
u
o
l
l
a
e
t
a
t
s
i
r
T
-
1
0
6
ICS9250-18
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
6
4
1
)
t
c
a
n
I
/
t
c
A
(
F
_
M
A
R
D
S
2
t
i
B
9
4
1
)
t
c
a
n
I
/
t
c
A
(
2
K
L
C
U
P
C
1
t
i
B
1
5
1
)
t
c
a
n
I
/
t
c
A
(
1
K
L
C
U
P
C
0
t
i
B
2
5
1
)
t
c
a
n
I
/
t
c
A
(
F
_
K
L
C
U
P
C
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
8
1
)
t
c
a
n
I
/
t
c
A
(
F
K
L
C
I
C
P
5
t
i
B
6
1
1
)
t
c
a
n
I
/
t
c
A
(
5
K
L
C
I
C
P
4
t
i
B
4
1
1
)
t
c
a
n
I
/
t
c
A
(
4
K
L
C
I
C
P
3
t
i
B
3
1
1
)
t
c
a
n
I
/
t
c
A
(
3
K
L
C
I
C
P
2
t
i
B
2
1
1
)
t
c
a
n
I
/
t
c
A
(
2
K
L
C
I
C
P
1
t
i
B
1
1
1
)
t
c
a
n
I
/
t
c
A
(
1
K
L
C
I
C
P
0
t
i
B
9
1
)
t
c
a
n
I
/
t
c
A
(
0
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
#
0
S
F
d
e
h
c
t
a
L
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
X
#
1
S
F
d
e
h
c
t
a
L
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
X
#
3
S
F
d
e
h
c
t
a
L
0
t
i
B
-
1
d
e
v
r
e
s
e
R
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
X
#
2
S
F
d
e
h
c
t
a
L
5
t
i
B
4
5
1
)
t
c
a
n
I
/
t
c
A
(
F
_
C
I
P
A
O
I
4
t
i
B
5
5
1
)
t
c
a
n
I
/
t
c
A
(
0
C
I
P
A
O
I
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
2
1
)
t
c
a
n
I
/
t
c
A
(
1
F
E
R
0
t
i
B
3
1
)
t
c
a
n
I
/
t
c
A
(
0
F
E
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
9
2
1
)
t
c
a
n
I
/
t
c
A
(
z
H
M
8
4
4
t
i
B
0
3
1
)
t
c
a
n
I
/
t
c
A
(
z
H
M
4
2
3
t
i
B
,
2
3
,
3
3
4
2
,
5
2
1
)
t
c
a
n
I
/
t
c
A
(
)
5
1
:
2
1
(
M
A
R
D
S
2
t
i
B
,
1
2
,
2
2
8
1
,
9
1
1
)
t
c
a
n
I
/
t
c
A
(
)
1
1
:
8
(
M
A
R
D
S
1
t
i
B
,
8
3
,
9
3
5
3
,
6
3
1
)
t
c
a
n
I
/
t
c
A
(
)
7
:
4
(
M
A
R
D
S
0
t
i
B
,
3
4
,
4
4
0
4
,
1
4
1
)
t
c
a
n
I
/
t
c
A
(
)
3
:
0
(
M
A
R
D
S
7
ICS9250-18
Third party brands and names are the property of their respective owners.
Shared Pin Operation -
Input/Output Pins
Fig. 1
The I/O pins designated by (input/output) on the ICS9250-
18 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 4-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
8
ICS9250-18
Third party brands and names are the property of their respective owners.
Fig. 2a
Fig. 2b
9
ICS9250-18
Third party brands and names are the property of their respective owners.
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9250-18. All other clocks will continue to run while the CPUCLKs are disabled. The
CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the
CPUCLKs inside the ICS9250-18.
3. IOAPIC output is stopped Glitch Free by CPUSTOP# going low.
4. PCI_STOP# is shown in a high (true) state.
5. All other clocks continue to run undisturbed.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the device.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9250-18. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9250-18 internally. PCICLK (0:5) clocks are stopped in a low state and started with a full
high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK
clock.
PCICLK (0:5)
IOAPIC0
SDRAM(0:15)
CPUCLK (1:2)
SDRAM_F
CPUCLK_F
PCI_STOP# (High)
CPU_STOP#
INTERNAL
CPUCLK
10
ICS9250-18
Third party brands and names are the property of their respective owners.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70 C; Supply Voltage V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating
I
DD2.5OP100
Select @ 100MHz; Max discrete cap loads
13
25
Supply Current
I
DD2.5OP133
Select @ 133MHz; Max discrete cap loads
18
25
1
Guaranteed by design, not 100% tested in production.
mA
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70 C; Supply Voltage V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+0.3
V
Input Low Voltage
V
IL
G
ND
-0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
0.1
5
A
Input Low Current
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
-5
2.0
A
Input Low Current
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
-100
A
Operating
I
DD3.3OP100
Select @ 100MHz; Sdram running
150
180
Supply Current
I
DD3.3OP133
Select @ 133MHz; Sdram running
200
n/a
Input frequency
F
i
V
DD
= 3.3 V
12
14.318
16
MHz
Input Capacitance
1
C
IN
Logic Inputs
5
pF
C
INX
X1 & X2 pins
27
36
45
pF
Transition Time
1
T
Trans
To 1st crossing of target Freq.
4
ms
Settling Time
1
T
S
From 1st crossing to 1% target Freq.
1
3
ms
Clk Stabilization
1
T
Stab
From V
DD
= 3.3 V to 1% target Freq.
4
ms
1
Guaranteed by design, not 100% tested in production.
mA
11
ICS9250-18
Third party brands and names are the property of their respective owners.
Electrical Characteristics - CPUCLK
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; C
L
= 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH2B
I
OH
= -12.0 mA
2
2.3
V
Output Low Voltage
V
OL2B
I
OL
= 12 mA
0.2
0.4
V
Output High Current
I
OH2B
V
OH
= 1.7 V
-41
-19
mA
Output Low Current
I
OL2B
V
OL
= 0.7 V
19
37
mA
Rise Time
t
r2B
1
V
OL
= 0.4 V, V
OH
= 2.0 V
0.4
1.6
ns
Fall Time
t
f2B
1
V
OH
= 2.0 V, V
OL
= 0.4 V
0.4
1
1.6
ns
Duty Cycle
d
t2B
1
V
T
= 1.25 V
45
51
55.5
%
Skew
group1: 1,2 and 1,F
t
sk2B
1
V
T
= 1.25 V
120
175
ps
Skew
group2: 2, F
t
sk2B
1
V
T
= 1.25 V
254
ps
Jitter, One Sigma
t
j1
2B
1
V
T
= 1.25 V
120
250
ps
Jitter, Absolute
t
jabs2B
1
V
T
= 1.25 V
-250
100
+250
ps
Jitter, Cycle-to-cycle
t
jcyc-cyc2B
1
V
T
= 1.25 V
150
250
ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz, 24MHz,REF0
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; C
L
= 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH5
I
OH
= -14 mA
2.4
2.9
V
Output Low Voltage
V
OL5
I
OL
= 6.0 mA
0.25
0.4
V
Output High Current
I
OH5
V
OH
= 2.0 V
-42
-20
mA
Output Low Current
I
OL5
V
OL
= 0.8 V
10
18
mA
Rise Time
1
t
r5
V
OL
= 0.4 V, V
OH
= 2.4 V
1.1
2.5
ns
Fall Time
1
t
f5
V
OH
= 2.4 V, V
OL
= 0.4 V
1
2.5
ns
Duty Cycle
1
d
t5
V
T
= 1.5 V
45
50
55
%
Jitter
1
t
j1s5
V
T
= 1.5 V, 24, 48MHz
100
250
ps
Jitter
1
t
jabs5
V
T
= 1.5 V, REF0
250
800
ps
1
Guaranteed by design, not 100% tested in production.
12
ICS9250-18
Third party brands and names are the property of their respective owners.
Electrical Characteristics - PCICLK
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; C
L
= 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH1
I
OH
= -18 mA
2.4
2.9
V
Output Low Voltage
V
OL1
I
OL
= 9.4 mA
0.2
0.4
V
Output High Current
I
OH1
V
OH
= 2.0 V
-58
-22
mA
Output Low Current
I
OL1
V
OL
= 0.8 V
25
52
mA
Rise Time
1
t
r1
V
OL
= 0.8 V, V
OH
= 2.4 V
1.5
2.5
ns
Fall Time
1
t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V
1.4
2.5
ns
Duty Cycle
1
d
t1
V
T
= 1.5 V
45
50
55
%
Skew
1
t
sk1
V
T
= 1.5 V
270
500
ps
Jitter, One Sigma
1
t
j1
1
V
T
= 1.5 V
50
150
ps
Jitter, Absolute
1
t
jabs1
V
T
= 1.5 V
200
500
ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; C
L
=30 pF
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH1
I
OH
= -28 mA
2.4
2.8
V
Output Low Voltage
V
OL1
I
OL
= 19 mA
0.34
0.4
V
Output High Current
I
OH1
V
OH
= 2.0 V
-72
-42
mA
Output Low Current
I
OL1
V
OL
= 0.8 V
33
50
mA
Rise Time
1
t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V
0.5
2
ns
Fall Time
1
t
f1
V
OH
= 2.4 V, V
OL
= 04 V
0.5
2.4
ns
Duty Cycle
1
d
t1
V
T
= 1.5 V
45
50
56.3
%
Skew(Group1: F,0:4, 8:11)
1
t
sk1
V
T
= 1.5 V
130
250
ps
Skew(Group2: 5:7, 12:15)
1
t
sk1
V
T
= 1.5 V
180
250
ps
Skew(Group3: 0, 13)
1
t
sk1
V
T
= 1.5 V
410
ps
Skew(Buferin-Output)
1
t
sk1
V
T
= 1.5 V
3.5
4.4
ns
Jitter, One Sigma
1
t
j1
1
V
T
= 1.5 V
50
150
ps
Jitter, Absolute
1
t
jabs1
V
T
= 1.5 V
-250
130
250
ps
1
Guaranteed by design, not 100% tested in production.
13
ICS9250-18
Third party brands and names are the property of their respective owners.
Electrical Characteristics - IOAPIC
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; C
L
= 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH4B
I
OH
= -12 mA
2
2.2
V
Output Low Voltage
V
OL4B
I
OL
= 12 mA
0.3
0.4
V
Output High Current
I
OH4B
V
OH
= 1.7 V
-32
-19
mA
Output Low Current
I
OL4B
V
OL
= 0.7 V
19
26
mA
Rise Time
1
T
r4B
V
OL
= 0.4 V, V
OH
= 2.0 V
0.4
1.5
1.8
ns
Fall Time
1
T
f4B
V
OH
= 2.0 V, V
OL
= 0.4 V
0.4
1
1.6
ns
Duty Cycle
1
D
t4B
V
T
= 1.25 V
45
51
55
%
Jitter, One Sigma
1
T
j1
4B
V
T
= 1.25 V
240
300
ps
Jitter, Absolute
1
T
jabs4B
V
T
= 1.25 V
619
650
ps
1
Guaranteed by design, not 100% tested in production.
14
ICS9250-18
Third party brands and names are the property of their respective owners.
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
Notes:
1) All clock outputs should have a
series terminating resistor, and a 20pF
capacitor to ground between the
resistor and clock pin. Not shown in
all places to improve readibility of
diagram.
2) Optional crystal load capacitors are
recommended. They should be
included in the layout but not
inserted unless needed.
Component Values:
C1 : Crystal load values determined by user
C2 : 22F/20V/D case/Tantalum
AVX TAJD226M020R
C3 : 100pF ceramic capacitor
C4 : 20pF capacitor
FB = Fair-Rite products 2512066017X1
All unmarked capacitors are 0.01F ceramic
Connections to VDD:
= Routed Power
= Ground Connection (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
Ferrite
Bead
VDD
C2
22F/20V
Tantalum
Ferrite
Bead
VDD
C2
22F/20V
Tantalum
C3
C3
1
Clock Load
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2
C1
C1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2.5V Power Route
3.3V Power Route
3.3V Power Route
Ground
Ground
15
ICS9250-18
Third party brands and names are the property of their respective owners.
L
O
B
M
Y
S
S
N
O
I
S
N
E
M
I
D
N
O
M
M
O
C
S
N
O
I
T
A
I
R
A
V
D
N
.
N
I
M
.
M
O
N
.
X
A
M
.
N
I
M
.
M
O
N
.
X
A
M
A
5
9
0
.
1
0
1
.
0
1
1
.
D
A
0
2
7
.
5
2
7
.
0
3
7
.
6
5
1
A
8
0
0
.
2
1
0
.
6
1
0
.
2
A
8
8
0
.
0
9
0
.
2
9
0
.
B
8
0
0
.
0
1
0
.
5
3
1
0
.
C
5
0
0
.
-
0
1
0
.
D
s
n
o
i
t
a
i
r
a
V
e
e
S
E
2
9
2
.
6
9
2
.
9
9
2
.
e
C
S
B
5
2
0
.
0
H
0
0
4
.
6
0
4
.
0
1
4
.
h
0
1
0
.
3
1
0
.
6
1
0
.
L
4
2
0
.
2
3
0
.
0
4
0
.
N
s
n
o
i
t
a
i
r
a
V
e
e
S
0
5
8
X
5
8
0
.
3
9
0
.
0
0
1
.
SSOP Package
Ordering Information
ICS9250yF-18
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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