Integrated
Circuit
Systems, Inc.
ICS932S208
0743D--07/07/04
Pin Configuration
Recommended Application:
CK409B clock, Intel Yellow Cover part, Server Applications
Output Features:
4 - 0.7V current-mode differential CPU pairs
1 - 0.7V current-mode differential SRC pair
7 - PCI (33MHz)
3 - PCICLK_F, (33MHz) free-running
1 - USB, 48MHz
1 - DOT, 48MHz
2 - REF, 14.318MHz
4 - 3V66, 66.66MHz
1 - VCH/3V66, selectable 48MHz or 66MHz
Key Specifications:
CPU/SRC outputs cycle-cycle jitter < 125ps
3V66 outputs cycle-cycle jitter < 250ps
PCI outputs cycle-cycle jitter < 250ps
CPU outputs skew: < 100ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
Programmable Timing Control HubTM for Next Gen P
4
TM processor
Functionality
Features/Benefits:
Supports tight ppm accuracy clocks for Serial-ATA
Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
Supports CPU clks up to 400MHz in test mode
Uses external 14.318MHz crystal
56-pin SSOP & TSSOP
B6b5 FS_A FS_B
CPU
MHz
SRC
MHz
3V66
MHz
PCI
MHz
REF
MHz
U
SB/DOT
MHz
0
0
100
100/200 66.66
33.33 14.318
48.00
0
MID
Ref/N
0
Ref/N
1
Ref/N
2
Ref/N
3
Ref/N
4
Ref/N
5
0
1
200
100/200 66.66
33.33 14.318
48.00
1
0
133
100/200 66.66
33.33 14.318
48.00
1
1
166
100/200 66.66
33.33 14.318
48.00
1
MID
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
200
100/200 66.66
33.33 14.318
48.00
0
1
400
100/200 66.66
33.33 14.318
48.00
1
0
266
100/200 66.66
33.33 14.318
48.00
1
1
333
100/200 66.66
33.33 14.318
48.00
0
1
REF0
1
56 FS_B
REF1
2
55 VDDA
VDDREF
3
54 GNDA
X1
4
53 GND
X2
5
52 IREF
GND
6
51 FS_A
PCICLK_F0
7
50 CPUCLKT3
PCICLK_F1
8
49 CPUCLKC3
PCICLK_F2
9
48 VDDCPU
VDDPCI 10
47 CPUCLKT2
GND 11
46 CPUCLKC2
PCICLK0 12
45 GND
PCICLK1 13
44 CPUCLKT1
PCICLK2 14
43 CPUCLKC1
PCICLK3 15
42 VDDCPU
VDDPCI 16
41 CPUCLKT0
GND 17
40 CPUCLKC0
PCICLK4 18
39 GND
PCICLK5 19
38 SRCCLKT
PCICLK6 20
37 SRCCLKC
PD# 21
36 VDD
3V66_0 22
35 Vtt_PWRGD#
3V66_1 23
34 VDD48
VDD3V66 24
33 GND
GND 25
32 48MHz_DOT
3V66_2 26
31 48MHz_USB
3V66_3 27
30 SDATA
SCLK 28
29 3V66_4/VCH
I
C
S
932
S
2
08
2
Integrated
Circuit
Systems, Inc.
ICS932S208
0743D--07/07/04
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
REF0
OUT
14.318 MHz reference clock.
2
REF1
OUT
14.318 MHz reference clock.
3
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
4
X1
IN
Crystal input, Nominally 14.318MHz.
5
X2
OUT
Crystal output, Nominally 14.318MHz
6
GND
PWR
Ground pin.
7
PCICLK_F0
OUT
Free running PCI clock not affected by PCI_STOP# .
8
PCICLK_F1
OUT
Free running PCI clock not affected by PCI_STOP# .
9
PCICLK_F2
OUT
Free running PCI clock not affected by PCI_STOP# .
10
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
11
GND
PWR
Ground pin.
12
PCICLK0
OUT
PCI clock output.
13
PCICLK1
OUT
PCI clock output.
14
PCICLK2
OUT
PCI clock output.
15
PCICLK3
OUT
PCI clock output.
16
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
17
GND
PWR
Ground pin.
18
PCICLK4
OUT
PCI clock output.
19
PCICLK5
OUT
PCI clock output.
20
PCICLK6
OUT
PCI clock output.
21
PD#
IN
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 1.8ms. Internal pull-up of 150K nominal.
22
3V66_0
OUT
3.3V 66.66MHz clock output
23
3V66_1
OUT
3.3V 66.66MHz clock output
24
VDD3V66
PWR
Power pin for the 3V66 clocks.
25
GND
PWR
Ground pin.
26
3V66_2
OUT
3.3V 66.66MHz clock output
27
3V66_3
OUT
3.3V 66.66MHz clock output
28
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
3
Integrated
Circuit
Systems, Inc.
ICS932S208
0743D--07/07/04
Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
29
3V66_4/VCH
OUT
66.66MHz clock output for AGP support. AGP-PCI should be aligned
with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.
30
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
31
48MHz_USB
OUT
48MHz clock output.
32
48MHz_DOT
OUT
48MHz clock output.
33
GND
PWR
Ground pin.
34
VDD48
PWR
Power pin for the 48MHz output.3.3V
35
Vtt_PWRGD#
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
36
VDD
PWR
Power supply for SRC clocks, nominal 3.3V
37
SRCCLKC
OUT
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
38
SRCCLKT
OUT
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
39
GND
PWR
Ground pin.
40
CPUCLKC0
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
41
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
42
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
43
CPUCLKC1
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
44
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
45
GND
PWR
Ground pin.
46
CPUCLKC2
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
47
CPUCLKT2
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
48
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
49
CPUCLKC3
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
50
CPUCLKT3
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
51
FS_A
IN
Frequency select pin, see Frequency table for functionality
52
IREF
OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
53
GND
PWR
Ground pin.
54
GNDA
PWR
Ground pin for core.
55
VDDA
PWR
3.3V power for the PLL core.
56
FS_B
IN
Frequency select pin, see Frequency table for functionality
4
Integrated
Circuit
Systems, Inc.
ICS932S208
0743D--07/07/04
ICS932S208 follows Intel CK409B Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS932S208 is driven with a 14.318MHz crystal. It generates CPU outputs
up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.
General Description
Block Diagram
Power Groups
I REF
PLL2
Frequency
Dividers
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
48MHz, USB, DOT
X1
X2
XTAL
SDATA
SCLK
Vtt_PWRGD#
PD#
FS_A
FS_B
Control
Logic
REF (1:0)
CPUCLKT (3:0)
CPUCLKC (3:0)
SRCCLKT0
SRCCLKC0
3V66(4:0)
PCICLK (6:0)
PCICLKF (2:0)
VDD
GND
3
6
Xtal, Ref
24
25
3V66 [0:3]
10,16
11,17
PCICLK outputs
36
39
SRCCLK outputs
55
54
Master clock, CPU Analog
34
33
48MHz, PLL
N/A
53
IREF
48, 42
45
CPUCLK clocks
Description
Pin Number
5
Integrated
Circuit
Systems, Inc.
ICS932S208
0743D--07/07/04
Absolute Max
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
V
DD
+ 0.5V
V
VDD_In
3.3V Logic Input Supply Voltage
GND - 0.5
V
DD
+ 0.5V
V
Ts
Storage Temperature
-65
150
C
Tambient
Ambient Operating Temp
0
70
C
Tcase Case
Temperature
115
C
ESD prot
Input ESD protection
human body model
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
V
IH
3.3 V +/-5%
2
V
DD
+ 0.3
V
Input MID Voltage
V
MID
3.3 V +/-5%
1
1.8
V
Input Low Voltage
V
IL
3.3 V +/-5%
V
SS
- 0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
-5
5
uA
I
IL1
V
IN
= 0 V; Inputs with no pull-up
resistors
-5
uA
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200
uA
Operating Supply Current
I
DD3.3OP
Full Active, C
L
= Full load;
350
mA
all diff pairs driven
35
mA
all differential pairs tri-stated
12
mA
Input Frequency
3
F
i
V
DD
= 3.3 V
14.31818
MHz
3
Pin Inductance
1
L
pin
7
nH
1
C
IN
Logic Inputs
5
pF
1
C
OUT
Output pin capacitance
6
pF
1
C
INX
X1 & X2 pins
5
pF
1
Clk Stabilization
1,2
T
STAB
From V
DD
Power-Up or de-
assertion of PD# to 1st clock
1.8
ms
1,2
Modulation Frequency
Triangular Modulation
30
33
kHz
1
Tdrive_SRC
SRC output enable after
PCI_Stop# de-assertion
15
ns
1
Tdrive_PD#
CPU output enable after
PD# de-assertion
300
us
1
Tfall_Pd#
PD# fall time of
5
ns
1
Trise_Pd#
PD# rise time of
5
ns
2
Tdrive_CPU_Stop#
CPU output enable after
CPU_Stop# de-assertion
10
us
1
Tfall_CPU_Stop#
PD# fall time of
5
ns
1
Trise_CPU_Stop#
PD# rise time of
5
ns
2
1
Guaranteed by design, not 100% tested in production.
2
See timing diagrams for timing requirements.
I
DD3.3PD
3
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
Input Capacitance
1
Input Low Current
Powerdown Current
PDF 
ZIP