Integrated
Circuit
Systems, Inc.
ICS93716
0420E--04/01/03
Block Diagram
Low Cost DDR Phase Lock Loop Clock Driver
Pin Configuration
28-Pin SSOP and TSSOP
Recommended Application:
DDR Clock Driver
Product Description/Features:
Low skew, low jitter PLL clock driver
I
2
C for functional and output control
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Switching Characteristics:
PEAK - PEAK jitter (66MHz): <120ps
PEAK - PEAK jitter (>100MHz): <75ps
CYCLE - CYCLE jitter (>100MHz):<65ps
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time: 650ps - 950ps
Functionality
S
T
U
P
N
I
S
T
U
P
T
U
O
e
t
a
t
S
L
L
P
D
D
V
A
T
N
I
_
K
L
C
C
N
I
_
K
L
C
T
K
L
C
C
K
L
C
T
T
U
O
_
B
F
C
T
U
O
_
B
F
V
5
.
2
)
m
o
n
(
L
H
L
H
L
H
n
o
V
5
.
2
)
m
o
n
(
H
L
H
L
H
L
n
o
V
5
.
2
)
m
o
n
(
z
H
M
0
2
<
Z
Z
Z
Z
f
f
o
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N
G
L
H
L
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L
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f
f
o
/
d
e
s
s
a
p
y
B
D
N
G
H
L
H
L
H
L
f
f
o
/
d
e
s
s
a
p
y
B
FB_INT
FB_INC
CLK_INC
CLK_INT
SCLK
SDATA
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
PLL
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLK_INT
CLK_INC
VDDA
GND
VDD
CLKT2
CLKC2
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
FBINC
FBINT
FB_OUTT
FB_OUTC
CLKT3
CLKC3
GND
ICS93716
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
ICS93716
0420E--04/01/03
Pin Descriptions
R
E
B
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V
5
,
t
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p
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s
C
3
ICS93716
0420E--04/01/03
Byte 0: Output Control
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
6
1
,
7
1
1
3
C
K
L
C
,
3
T
K
L
C
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
Byte 1: Output Control
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
Byte 3: Reserved
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
Byte 4: Reserved
(1= enable, 0 = disable)
Byte 2: Reserved
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 5: Reserved
(1= enable, 0 = disable)
Note: Don't write into this register, writing into this
register can cause malfunction
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
1
,
2
1
0
C
K
L
C
,
0
T
K
L
C
6
t
i
B
5
,
4
1
1
C
K
L
C
,
1
T
K
L
C
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
4
1
,
3
1
1
2
C
K
L
C
,
2
T
K
L
C
2
t
i
B
7
2
,
6
2
1
5
C
K
L
C
,
5
T
K
L
C
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
5
2
,
4
2
1
4
C
K
L
C
,
4
T
K
L
C
4
ICS93716
0420E--04/01/03
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . . -0.5V to 4.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to V
DD
+ 0.5V
Ambient Operating Temperature . . . . . . . . . . 0C to +85C
Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R
L
= 120
, C
L
=15pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Current
I
IH
V
I
= V
DD
or GND
5
A
Input Low Current
I
IL
V
I
= V
DD
or GND
5
A
I
DD2.5
R
L
= 120
, C
L
= 0pf @ 170MHz
250
350
mA
I
DDPD
C
L
= 0pf
65
90
mA
Input Clamp Voltage
V
IK
V
DDQ
= 2.3V Iin = -18mA
-1.2
V
I
OH
= -1 mA
V
DD
- 0.1
V
I
OH
= -12 mA
1.7
V
I
OL
=1 mA
0.1
V
I
OL
=12 mA
0.6
V
Input Capacitance
1
C
IN
V
I
= GND or V
DD
3
pF
Output Capacitance
1
C
OUT
V
OUT
= GND or V
DD
3
pF
1
Guaranteed by design at 233MHz, not 100% tested in production.
Operating Supply
Current
High-level output
voltage
V
OH
Low-level output voltage
V
OL
5
ICS93716
0420E--04/01/03
DC Electrical Characteristics (see note1)
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
V
DDQ
, A
VDD
2.3
2.5
2.7
V
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.4
V
DD
/2 - 0.18
V
SCLK, SDATA
-0.3
0.7
V
CLK_INT, CLK_INC, FB_INC,
FB_INT
V
DD
/2 + 0.18
2.1
V
SCLK, SDATA
1.7
5
V
DC input signal voltage
(note 2)
V
IN
-0.3
V
DD
+ 0.3
V
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.36
V
DD
+ 0.6
V
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.7
V
DD
+ 0.6
V
Output differential cross-
voltage (note 4)
V
OX
V
DD
/2 - 0.15
V
DD
/2 + 0.15
V
Input differential cross-
voltage (note 4)
V
IX
V
DD
/2 - 0.2
V
DD
/2
V
DD
/2 + 0.2
V
High Impedance
Output Current
I
OZ
V
DD
=2.7V, V
OUT
=V
DD
or GND
0.1
5
A
Operating free-air
temperature
T
A
0
85
C
Differential input signal
voltage (note 3)
V
ID
Low level input voltage
V
IL
High level input voltage
V
IH
Notes:
1.
Unused inputs must be held high or low to prevent them from floating.
2.
DC input signal voltage specifies the allowable DC excursion of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4.
Differential cross-point voltage is expected to track variations of V
DD
and is the
voltage at which the differential signal crosses.
6
ICS93716
0420E--04/01/03
Notes:
1.
Refers to transition on noninverting output in PLL bypass mode.
2.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t
wH
/t
c
, were
the cycle (t
c
) decreases as the frequency goes up.
3.
Switching characteristics guaranteed for application frequency range.
4.
Static phase offset shifted by design.
Timing Requirements
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R
L
= 120
, C
L
=15pF (unless otherwise
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
3
freq
op
33
233
MHz
Application Frequency
Range
3
freq
App
60
170
MHz
Input clock duty cycle
d
tin
40
60
%
CLK stabilization
T
STAB
100
s
Switching Characteristics
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R
L
= 120
, C
L
=15pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level
propagation delay time
t
PLH
1
CLK_IN to any output
5.5
ns
High-to low level propagation
delay time
t
PHL
1
CLK_IN to any output
5.5
ns
Duty Cycle
DC
49
51
%
Input clock slew rate
t
sl(I)
1
4
v/ns
Cycle to Cycle Jitter
1
t
cyc
-t
cyc
66/100/125/133/167MHz
75
ps
Phase error
t
(phase error)
4
-150
0
50
ps
Output to Output Skew
t
skew
75
100
ps
Rise Time, Fall Time
t
r
, t
f
See figure 8
650
950
ps
7
ICS93716
0420E--04/01/03
GND
ICS93716
V
DD
VDD /2
V(CLKC)
V(CLKC)
SCOPE
C = 16 pF
-VDD/2
-VDD/2
-VDD/2
VDD/2
Z = 60
Z = 60
Z = 50
Z = 50
R = 10
R = 10
R = 50
R = 60
R = 60
R = 50
V(TT)
V(TT)
C = 16 pF
NOTE: V(TT) = GND
tc(n)
tc(n+1)
tjit(cc) = tc(n) tc(n+1)
Figure 1. IBIS Model Output Load
Figure 2. Output Load Test Circuit
Y , FB_OUTC
X
Y , FB_OUTT
X
Parameter Measurement Information
ICS93716
Figure 3. Cycle-to-Cycle Jitter
8
ICS93716
0420E--04/01/03
(N is a large number of samples)
t ( ) n+1
t ( ) n
t ( )=
1
n = N
t ( ) n
N
CLK_INC
CLK_INT
FB_INC
FB_INT
t
(skew)
Y #
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y
X
Parameter Measurement Information
Figure 4. Static Phase Offset
Figure 5. Output Skew
1
f
O
t
=
t
-
(jit_per)
t
c(n)
C(n)
1
f
O
Figure 6. Period Jitter
9
ICS93716
0420E--04/01/03
Clock Inputs
and Outputs
80%
20%
80%
20%
tslr
tslf
VID, VOD
Figure 8. Input and Output Slew Rates
Parameter Measurement Information
tjit(hper_n)
tjit(hper_n+1)
1
fo
Y , FB_OUTC
X
Y , FB_OUTT
X
Figure 7. Half-Period Jitter
t
jit(hper)
t
jit(hper_n)
1
2xf
O
=
-
10
ICS93716
0420E--04/01/03
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Write:
11
ICS93716
0420E--04/01/03
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
- C -
- C -
b
.10 (.004) C
.10 (.004) C
c
L
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
E1
E
Ordering Information
ICS93716yF-T
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
Example:
ICS XXXXX y F - T
MIN
MAX
MIN
MAX
A
--
2.00
--
.079
A1
0.05
--
.002
--
A2
1.65
1.85
.065
.073
b
0.22
0.38
.009
.015
c
0.09
0.25
.0035
.010
D
E
7.40
8.20
.291
.323
E1
5.00
5.60
.197
.220
e
L
0.55
0.95
.022
.037
N
0
8
0
8
VARIATIONS
MIN
MAX
MIN
MAX
28
9.90
10.50
.390
.413
10-0033
Reference Doc.: JEDEC Publication 95, MO-150
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
SEE VARIATIONS
SEE VARIATIONS
0.65 BASIC
0.0256 BASIC
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
12
ICS93716
0420E--04/01/03
Ordering Information
ICS93716yG-T
Example:
ICS XXXXX y G - T
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
- C -
- C -
b
c
L
aaa
C
6.10 mm. Body, 0.65 mm. pitch TSSOP
(240 mil)
(25.6 mil)
MIN
MAX
MIN
MAX
A
--
1.20
--
.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.012
c
0.09
0.20
.0035
.008
D
E
E1
6.00
6.20
.236
.244
e
L
0.45
0.75
.018
.030
N
0
8
0
8
aaa
--
0.10
--
.004
VARIATIONS
MIN
MAX
MIN
MAX
28
9.60
9.80
.378
.386
10-0039
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
SEE VARIATIONS
SEE VARIATIONS
8.10 BASIC
0.319 BASIC
0.65 BASIC
0.0256 BASIC
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
Reference Doc.: JEDEC Publication 95, MO-153
Designation for tape and reel packaging
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
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