Integrated
Circuit
Systems, Inc.
ICS93720
Preliminary Product Preview
Block Diagram
DDR Phase Lock Loop Clock Driver
93720 Rev C 07/05/01
Pin Configuration
48-Pin TSSOP
Recommended Application:
DDR Clock Driver
Product Description/Features:
Low skew, low jitter PLL clock driver
I
2
C for functional and output control
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Bypass mode mux
Switching Characteristics:
PEAK - PEAK jitter (66MHz): <120ps
PEAK - PEAK jitter (>100MHz): <75ps
CYCLE - CYCLE jitter (66MHz):<120ps
CYCLE - CYCLE jitter (>100MHz):<65ps
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
PLL
FB_INT
FB_INC
CLK_INC
CLK_INT
SCLK
SDATA
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKT6
CLKT7
CLKT8
CLKT9
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
CLKC6
CLKC7
CLKC8
CLKC9
Control Bit
Functionality
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PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
2
ICS93720
Preliminary Product Preview
Pin Descriptions
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3
ICS93720
Preliminary Product Preview
Byte 0: Output Control
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
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5
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4
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-
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R
1
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v
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s
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R
0
t
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B
-
0
d
e
v
r
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s
e
R
Byte 1: Output Control
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
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D
7
t
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B
-
1
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R
6
t
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1
d
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5
t
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-
1
d
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R
4
t
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-
1
d
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R
3
t
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B
-
1
d
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v
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R
2
t
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B
-
1
d
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v
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s
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R
1
t
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B
-
1
d
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v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
Byte 3: Reserved
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
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D
7
t
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B
-
1
d
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e
R
6
t
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B
-
1
d
e
v
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s
e
R
5
t
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B
-
1
d
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v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
Byte 4: Reserved
(1= enable, 0 = disable)
Byte 2: Reserved
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
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s
e
R
4
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 5: Reserved
(1= enable, 0 = disable)
Note: Don't write into this register, writing into this
register can cause malfunction
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
2
,
3
1
0
C
K
L
C
,
0
T
K
L
C
6
t
i
B
6
,
5
1
1
C
K
L
C
,
1
T
K
L
C
5
t
i
B
9
,
0
1
1
2
C
K
L
C
,
2
T
K
L
C
4
t
i
B
9
1
,
0
2
1
3
C
K
L
C
,
3
T
K
L
C
3
t
i
B
3
2
,
2
2
1
4
C
K
L
C
,
4
T
K
L
C
2
t
i
B
7
4
,
6
4
1
5
C
K
L
C
,
5
T
K
L
C
1
t
i
B
3
4
,
4
4
1
6
C
K
L
C
,
6
T
K
L
C
0
t
i
B
0
4
,
9
3
1
7
C
K
L
C
,
7
T
K
L
C
4
ICS93720
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . . . . -0.5V to 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0C to +85C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Com m on Output Param eters
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (un less otherwise stated)
PARAM ETER
SYM BOL
CONDITIONS
M IN
TYP
M AX
UNITS
Inpu t Hig h Curren t
I
IH
VI = VDD or GND
A
Inpu t Low Current
I
IL
VI = VDD or GND
A
I
DD2 .5
CL = 0pf
mA
I
DDPD
CL = 0pf
100
A
Outpu t Hig h Curren t
I
OH
VDD = 2.3V, V
OUT
= 1 V
-18
mA
Outpu t Low Current
I
OL
VDD = 2.3V, V
OUT
= 1 .2V
26
mA
High Impedance
Outpu t Current
I
OZ
VDD=2.7 V, Vou t=VDD or GND
10
A
Inpu t Clamp Voltag e
V
IK
Iin = -18mA
V
VDD = min to max,
IOH = -1 mA
V
VDD = 2.3V,
IOH = -12 mA
V
VDD = min to max
I
OL
=1 mA
0.1
VDD = 2.3V
IOH=12 mA
0.6
V
Inpu t Capacitance
1
C
IN
VI = GND or VDD
pF
Outpu t Capacitance
1
C
OUT
VOUT = GND or VDD
3
pF
1
Guaranteed by design, not 10 0% tested in productio n.
Operating Supply Current
High-level output
vo ltage
V
OH
Low-level outpu t voltage
V
OL
Recom m ended Ope rating Condition
T
A
= 0 - 85C; Supply Vo ltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAM ETER
SYM BOL
CONDITIONS
M IN
TYP
M AX
UNITS
Analog/core supply
voltage
A
VDD
2.3
2.5
2.7
V
Input voltage level
V
IN
V
Input differential-pair
crossing voltage
V
IC
V
Output differential-pair
crossing voltage
V
OC
V
1
Guaranteed by design, not 100% tested in production.
5
ICS93720
Preliminary Product Preview
Notes:
1.
Refers to transition on noninverting output.
2.
While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=t
wH
/t
c
, were the cycle (t
c
)
decreases as the frequency goes up.
Tim ing Requirem ents
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAM ETER
SYM BOL
CONDITIONS
M IN
M AX
UNITS
Operating clock frequency
freq
o p
66
200
M Hz
Input clock duty cycle
d
tin
40
60
%
CLK stabilization
T
STAB
from VDD = 3.3V to 1%
target freq.
100
s
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
66MHz
120
ps
100/125/133/167MHz
75
ps
66MHz
110
ps
100/125/133/167MHz
65
ps
Phase error
t
(phase error)
-150
150
ps
Output to Output Skew
T
skew
100
ps
Pulse skew
T
skewp
100
ps
66MHz to 100MHz
49.5
50.5
%
101MHz to 167MHz
49
51
%
Rise Time, Fall Time
tr, tf
Load = 120
/16pF
650
800
950
ps
Typ: Propagation Delay Time
Bypass Mode CLK to
any output
4
ns
Duty cycle
D
C
2
Jitter; Absoulte Jitter
T
jabs
Cycle to Cycle Jitter1
T
cyc
-T
cyc
6
ICS93720
Preliminary Product Preview
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Write:
7
ICS93720
Preliminary Product Preview
Recommended Layout for the ICS93720
General Layout Precautions:
Use copper flooded ground on the top signal layer under the
clock buffer The area under U1 on the right is an example.
Flood over the ground vias.
1)
Use power vias for power and ground. Vias 20 mil or
larger in diameter have lower high frequency impedance.
Vias for signals may be minimum drill size.
2)
Make all power and ground traces are as wide as the via
pad for lower inductance.
3)
VAA for pin 16 has a low pass RC filter to decouple the
digital and analog supplies. The 4.7uF capacitors may be
replaced with a single low ESR device with the same
total capacitance. VAA is routed on a outside signal
layer. Do not cut a power or ground plane and route in it.
4)
Notice that ground vias are never shared.
5)
When ever possible, VCC (net V2P5 in the schematic)
pins have a decoupling capacitor. Power is always routed
from the plane connection via to the capacitor pad to the
VCC pin on the clock buffer. Moats or plane cuts are not
used to isolate power.
6)
Differential mode clock output traces are routed:
a.
With a ground trace between the pairs. Trace is
grounded on both ends.
b.
Without a ground trace, clock pairs are routed with a
separation of at least 5 times the thickness of the
dielectric. If the dielectric thickness is 4.5 mil, the
trace separation is at least 18 mils.
Component Values:
Ref Desg.
Value
Description
Package
C1,C4,C5,
C7,C11,C12
.01uF
CERAMIC MLC
0603
C2,C3,C8,
C9
4.7uF
CERAMIC MLC
1206
C10
.22uF
CERAMIC MLC
0603
C6
2200pF
CERAMIC MLC
0603
R12
120
0603
R9
4.7
0603
U1
ICS93701AG
TSSOP48
C2
4.7uF
1
2
V2P5
FB_IN#
C3
4.7uF
1
2
V2A5
C9
4.7uF
1
2
C7
.01uF
1
2
V2P5
C16
.01uF
1
2
C10
.22uF
1
2
C1
.01uF
1
2
C5
.01uF
1
2
C11
.01uF
1
2
R12
120
1
2
V2A5
V2A5
CLK_IN#
U1
ICS93701
16
4
11
15
21
28
34
38
45
1
7
8
18
24
25
31
41
42
48
17
35
36
13
14
37
12
3
2
5
6
10
9
20
19
22
23
46
47
44
43
39
40
29
30
27
26
33
32
AVDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AGND
FB_INT
FB_INC
CLK_INT
CLK_INC
SDA
SCL
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
FB_OUTT
FB_OUTC
C12
.01uF
1
2
C6
.0022pF
1
2
SCL
R9
4.7
1
2
C13
.01uF
1
2
SDA
C14
.01uF
1
2
FB_IN
C8
4.7uF
1
2
C15
.01uF
1
2
CLK_IN
C4
.01uF
1
2
8
ICS93720
Preliminary Product Preview
Ordering Information
ICS93720yGT
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y G - PPP - T
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
- C -
- C -
b
c
L
aaa
C
6.10 mm. Body, 0.50 mm. pitch TSSOP
(240 mil)
(0.020 mil)
MIN
MAX
MIN
MAX
A
--
1.20
--
.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
D
E
E1
6.00
6.20
.236
.244
e
L
0.45
0.75
.018
.030
N
0
8
0
8
aaa
--
0.10
--
.004
VARIATIONS
MIN
MAX
MIN
MAX
48
12.40
12.60
.488
.496
10-0039
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
SEE VARIATIONS
SEE VARIATIONS
8.10 BASIC
0.319 BASIC
0.50 BASIC
0.020 BASIC
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
Reference Doc.: JEDEC Publication 95, MO-153
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