Integrated
Circuit
Systems, Inc.
ICS93725
0606A--08/01/03
Block Diagram
DDR and SDRAM Zero Delay Buffer
Pin Configuration
48-Pin SSOP
Recommended Application:
DDR & SDRAM Zero Delay Buffer for SIS 635/640/645/
650 & 735/740/746 style chipsets.
Product Description/Features:
Low skew, Zero Delay Buffer
1 to 13 SDRAM PC133 clock distribution
1 to 6 pairs of DDR clock distribution
I
2
C for functional and output control
Separate feedback path for both memory mode to
adjust synchronization.
Supports up to 2 DDR DIMMs or 3 SDRAM DIMMs
Frequency support for up to 200MHz
Individual I
2
C clock stop for power mananagement
CMOS level control signal input
Switching Characteristics:
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time for DDR outputs: 550ps -
1150ps
DUTY CYCLE: 47% - 53%
*Internal Pull-up Resistor of 120K to VDD
Functionality
E
D
O
M
8
4
N
I
P
D
D
V
5
.
2
_
3
.
3
R
D
D
e
d
o
M
1
=
R
D
D
_
L
E
S
V
5
.
2
D
S
/
R
D
D
e
d
o
M
0
=
R
D
D
_
L
E
S
V
3
.
3
VDD3.3
SDRAM0
SDRAM1
SDRAM2
SDRAM3
GND
VDD3.3
SDRAM4
SDRAM5
BUFFER_IN
SDRAM6
SDRAM7
GND
VDD3.3
SDRAM8
SDRAM9
SDRAM10
SDRAM11
GND
VDD3.3
SDRAM12
SDFB_OUT
SDFB_IN
GND
SEL_DDR*
DDRFB_IN
DDRFB_OUT
VDD2.5
DDRT5
DDRC5
DDRT4
DDRC4
GND
VDD2.5
DDRT3
DDRC3
DDRT2
DDRC2
GND
VDD2.5
DDRT1
DDRC1
DDRT0
DDRC0
GND
VDD2.5
SCLK
SDATA
ICS93725
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL_DDR*
PLL1
SDRAM (12:0)
DDRFB_OUT
SDRAMFB_OUT
BUFFER_IN
SDRAMFB_IN
DDRFB_IN
SDATA
SCLK
Control
Logic
Config.
Reg.
3
3
DDRT (5:0)
DDRCC (5:0)
2
ICS93725
0606A--08/01/03
Pin Descriptions
R
E
B
M
U
N
N
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M
A
N
N
I
P
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P
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1
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1
3
.
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6
0
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8
2
D
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8
,
9
,
1
1
,
2
1
2
,
3
,
4
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0
:
2
1
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6
2
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e
d
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R
D
D
=
1
e
d
o
m
D
S
=
0
3
ICS93725
0606A--08/01/03
Byte 6: Output Control
(1= enable, 0 = disable)
Byte 7: Output Control
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
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R
C
S
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D
7
t
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B
8
4
-
)
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c
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R
(
R
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S
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
3
4
,
4
4
1
5
C
R
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D
,
5
T
R
D
D
3
t
i
B
1
4
,
2
4
1
4
C
R
D
D
,
4
T
R
D
D
2
t
i
B
7
3
,
8
3
1
3
C
R
D
D
,
3
T
R
D
D
1
t
i
B
5
3
,
6
3
1
2
C
R
D
D
,
2
T
R
D
D
0
t
i
B
1
3
,
2
3
1
1
C
R
D
D
,
1
T
R
D
D
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
9
2
,
0
3
1
0
C
R
D
D
,
0
T
R
D
D
6
t
i
B
1
2
1
2
1
M
A
R
D
S
5
t
i
B
8
1
,
7
1
1
0
1
M
A
R
D
S
1
1
M
A
R
D
S
4
t
i
B
6
1
,
5
1
1
8
M
A
R
D
S
9
M
A
R
D
S
3
t
i
B
2
1
,
1
1
1
6
M
A
R
D
S
7
M
A
R
D
S
2
t
i
B
9
,
8
1
4
M
A
R
D
S
5
M
A
R
D
S
1
t
i
B
5
,
4
1
2
M
A
R
D
S
3
M
A
R
D
S
0
t
i
B
3
,
2
1
1
M
A
R
D
S
0
M
A
R
D
S
4
ICS93725
0606A--08/01/03
Absolute Maximum Ratings
Supply Voltage (VDD & VDD2.5) . . . . . . . . . -0.5V to 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . 0C to +85C
Case Temperature . . . . . . . . . . . . . . . . . . . . . 115C
Storage Temperature . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
SEL_DDR=0 SDRAM Outputs V
DD
=3.3V, T
A
=0 - 85C; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
100MHz, RL=0
, CL = 0pF
130
133MHz, RL=0
,
CL = 0pF
173
mA
200MHz, RL=0
, CL = 0pF
247
mA
Output High Current
I
OH
V
DD
=3.3V, V
OUT
=1V
-40
-18
mA
Output Low Current
I
OL
V
DD
=3.3V, V
OUT
=1.2V
26
34
mA
V
DD
=3.3V
I
OH
= -12 mA
V
DD
=3.3V
I
OH
= 12 mA
Input Capacitance
1
C
IN
V
I
= GND or V
DD
2
pF
1
Guaranteed by design, not 100% tested in production.
V
OH
High-level output voltage
Operating Supply Current
I
DD3.3
V
2
1.7
0.4
0.6
Low-level output voltage
V
V
OL
Recommended Operating Condition
SEL_DDR=0 SDRAM Outputs V
DD
=3.3V, T
A
=0 - 85C; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply Voltage
V
DD3.3
3
3.3
3.6
V
Input High Voltage
V
IH
SEL_DDR, PD# input
2
V
Input Low Voltae
V
IL
SEL_DDR, PD# input
0.8
V
Input Voltage Level
V
IN
0
3.3
3.6
V
1
Guaranteed by design, not 100% tested in production.
5
ICS93725
0606A--08/01/03
Electrical Characteristics - Input/Supply/Common Output Parameters
SEL_DDR=1 DDR Outputs V
DD
=2.5V, T
A
=0 - 85C; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
100MHz, RL=0
, CL = 0pF
141
mA
133MHz, RL=0
,
CL = 0pF
188
mA
200MHz, RL=0
, CL = 0pF
271
mA
Output High Current
I
OH
V
DD
=2.5V, V
OUT
=1V
-43
-18
mA
Output Low Current
I
OL
V
DD
=2.5V, V
OUT
=1.2V
26
38
mA
V
DD
=2.5V
I
OH
= -12 mA
V
DD
=2.5V
I
OH
= 12 mA
Output differential-pair
V
DD
= 2.5V
Crossing voltage
100/133/166/ 200 Mhz
Input Capacitance
1
C
IN
V
I
= GND or V
DD
2
pF
1
Guaranteed by design, not 100% tested in production.
V
OH
1.7
I
DD2.5
Operating Supply Current
2
V
Low-level output voltage
V
OL
0.4
0.6
V
High-level output voltage
1.45
V
V
OC
1.05
1.25
Recommended Operating Condition
SEL_DDR=1 DDR Outputs V
DD
=2.5V, T
A
=0 - 85C; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply Voltage
V
DD2.5
2.3
2.5
2.7
V
Input High Voltage
V
IH
SEL_DDR, PD# input
2
V
Input Low Voltage
V
IL
SEL_DDR, PD# input
0.8
V
Input Voltage Level
V
IN
0
2.5
2.7
V
1
Guaranteed by design, not 100% tested in production.
6
ICS93725
0606A--08/01/03
Switching Waveforms
Duty Cycle Timing
t
1
t
2
1.5V
1.5V
1.5V
SDRAM Buffer LH and HL Propagation Delay
INPUT
OUTPUT
t
6
t
7
Switching Characteristics
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Frequency
66
200
MHz
Input Clock Duty Cycle
d
in
40
60
%
DDR Static Phase Error
tped
-100
-50
100
ps
SDRAM Static Phase Error
tpes
-100
-20
100
ps
Not including FBOUT
to outputs
Not including FBOUT
to outputs
66MHz to 100MHz
48
52
%
101MHz to 200MHz
48
53
%
66MHz to 100MHz
48
52
%
101MHz to 200MHz
48
56
%
DDR Rise Time
trd
Measured between
0.55
0.68
0.95
ns
DDR Fall Time
tfd
20% and 80% output, CL=16pF
0.63
0.91
1.15
ns
SDRAM Rise Time
trs
0.5
1.4
1.7
ns
SDRAM Fall Time
tfs
0.5
1.65
1.8
ns
DDR Cycle to Cycle Jitter
t(
C-C)D
SEL_DDR=1,V
DD
=2.5V ,
CL=16pF
23
38
ps
SDRAM Cycle to Cycle Jitter
t
(C-C)S
SEL_DDR=0,V
DD
=3.3V ,
CL=30pF
36
57
ps
1
Guaranteed by design, not 100% tested in production.
2
While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=t
2
/t
1
, where the cycle (t
1
) decreases
as the frequency goes up.
200
DDR output to output Skew
T
skewd
60
ps
300
100
ps
SDRAM Duty Cycle
D
C
2
V
OL
= 0.4V, V
OH
= 2.4V,
CL=30pF
DDR Duty Cycle
D
C
2
SDRAM output to output Skew
T
skews
7
ICS93725
0606A--08/01/03
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D4
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 7
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D5
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 7
Stop Bit
How to Read:
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D4
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 6
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D5
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 7
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
8
ICS93725
0606A--08/01/03
Ordering Information
ICS93725yFT
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
Example:
ICS XXXX y F - T
300 mil SSOP Package
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.03
10.68
.395
.420
E1
7.40
7.60
.291
.299
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
0
8
0
8
MIN
MAX
MIN
MAX
48
15.75
16.00
.620
.630
10-0034
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
SEE VARIATIONS
SEE VARIATIONS
0.635 BASIC
0.025 BASIC
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
h x 45
h x 45
E1
E
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
- C -
b
.10 (.004) C
.10 (.004) C
c
L
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