Integrated
Circuit
Systems, Inc.
ICS93738
0689A--01/09/03
Block Diagram
DDR and SDRAM Buffer
Pin Configuration
48-Pin SSOP
Recommended Application:
DDR & SDRAM fanout buffer, for VIA P4X/KT266/333
chipsets.
Product Description/Features:
Low skew, fanout buffer
1 to 12 differential clock distribution
I
2
C for functional and output control
Feedback pin for input to output synchronization
Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs
+ 2 DDR DIMMs
Frequency supports up to 200MHz (DDR400)
Supports Power Down Mode for power
mananagement
CMOS level control signal input
Switching Characteristics:
OUTPUT - OUTPUT skew: <100ps SDRAM
OUTPUT - OUTPUT skew: <150ps DDR
Output Rise and Fall Time for DDR outputs: 600ps -
950ps
DUTY CYCLE: 47% - 53% DDR
DUTY CYCLE: 45%- 55% SDRAM
*Internal Pull-up Resistor of 120K to VDD
SCLK
SDATA
SEL_DDR*
PD#
BUF_IN
Control
Logic
FB_OUT
DDRT0_SDRAM0
DDRT1_SDRAM2
DDRT2_SDRAM4
DDRT3_SDRAM6
DDRT4_SDRAM8
DDRT5_SDRAM10
DDRT(11:6)
DDRC0_SDRAM1
DDRC1_SDRAM3
DDRC2_SDRAM5
DDRC3_SDRAM7
DDRC4_SDRAM9
DDRC5_SDRAM11
DDRC (11:6)
Functionality
E
D
O
M
8
4
N
I
P
D
D
V
5
.
2
_
3
.
3
N
I
P
,
5
1
,
1
1
,
0
1
,
7
,
6
,
5
,
4
2
2
,
1
2
,
0
2
,
9
1
,
6
1
R
D
D
e
d
o
M
1
=
R
D
D
_
L
E
S
V
5
.
2
e
b
ll
i
w
s
t
u
p
t
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h
T
s
t
u
p
t
u
o
R
D
D
D
S
/
R
D
D
e
d
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0
=
R
D
D
_
L
E
S
V
3
.
3
e
b
ll
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w
s
t
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p
t
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M
A
R
D
S
d
r
a
d
n
a
t
s
s
t
u
p
t
u
o
FB_OUT
VDD3.3_2.5
GND
DDRT0_SDRAM0
DDRC0_SDRAM1
DDRT1_SDRAM2
DDRC1_SDRAM3
VDD3.3_2.5
GND
DDRT2_SDRAM4
DDRC2_SDRAM5
VDD3.3_2.5
BUF_IN
GND
DDRT3_SDRAM6
DDRC3_SDRAM7
VDD3.3_2.5
GND
DDRT4_SDRAM8
DDRC4_SDRAM9
DDRT5_SDRAM10
DDRC5_SDRAM11
VDD3.3_2.5
SDATA
SEL_DDR*
VDD2.5
GND
DDRT11
DDRC11
DDRT10
DDRC10
VDD2.5
GND
DDRT9
DDRC9
VDD2.5
PD#*
GND
DDRT8
DDRC8
VDD2.5
GND
DDRT7
DDRC7
DDRT6
DDRC6
GND
SCLK
ICS93738
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2
ICS93738
0689A--01/09/03
Pin Descriptions
R
E
B
M
U
N
N
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A
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N
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D
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=
1
e
d
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m
D
S
/
R
D
D
=
0
3
ICS93738
0689A--01/09/03
Byte 6: Output Control
(1= enable, 0 = disable)
Byte 7: Output Control
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
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T
P
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C
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D
7
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(
R
D
D
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S
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B
4
4
,
5
4
1
1
1
C
R
D
D
,
1
1
T
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D
D
2
t
i
B
2
4
,
3
4
1
0
1
C
R
D
D
,
0
1
T
R
D
D
1
t
i
B
8
3
,
9
3
1
9
C
R
D
D
,
9
T
R
D
D
0
t
i
B
3
3
,
4
3
1
8
C
R
D
D
,
8
T
R
D
D
T
I
B
#
N
I
P
D
W
P
N
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I
T
P
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C
S
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D
7
t
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B
9
2
,
0
3
1
7
C
R
D
D
,
7
T
R
D
D
6
t
i
B
7
2
,
8
2
1
6
C
R
D
D
,
6
T
R
D
D
5
t
i
B
2
2
,
1
2
1
0
1
M
A
R
D
S
,
5
T
R
D
D
1
1
M
A
R
D
S
_
5
C
R
D
D
4
t
i
B
0
2
,
9
1
1
8
M
A
R
D
S
_
4
T
R
D
D
9
M
A
R
D
S
_
4
C
R
D
D
3
t
i
B
6
1
,
5
1
1
6
M
A
R
D
S
_
3
T
R
D
D
7
M
A
R
D
S
_
3
C
R
D
D
2
t
i
B
1
1
,
0
1
1
4
M
A
R
D
S
_
2
T
R
D
D
5
M
A
R
D
S
_
2
C
R
D
D
1
t
i
B
7
,
6
1
2
M
A
R
D
S
_
1
T
R
D
D
3
M
A
R
D
S
_
1
C
R
D
D
0
t
i
B
5
,
4
1
1
M
A
R
D
S
_
0
T
R
D
D
0
M
A
R
D
S
_
0
C
R
D
D
4
ICS93738
0689A--01/09/03
Absolute Maximum Ratings
Supply Voltage (VDD & VDD2.5) . . . . . . . . -0.5V to 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . 0C to +85C
Case Temperature . . . . . . . . . . . . . . . . . . . . 115C
Storage Temperature . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above
those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Electrical Characteristics - Input / Supply / Common Output Parameters - SDRAM
SEL_DDR=0, SDRAM Outputs, V
DD3.3_2.5
= 3.3V, T
A
= 0 - 85
o
C (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Current
I
IH
V
IN
= V
DD
or GND
10
A
Input Low Current
I
IL
V
IN
= V
DD
or GND
-100
A
I
DD3.3_2.5
C
L
= 0 pF at 133 MHz
170
250
mA
I
DD2.5
C
L
= 0 pF at 133 MHz
90
200
mA
I
DDPD
C
L
= 0 pF
0
10
A
Output High Current
I
OH
V
DD
= 3.3V, V
OUT
= 1V
-18
mA
Output Low Current
I
OL
V
DD
= 3.3V, V
OUT
= 1.2V
26
mA
High-level Output Voltage
V
OH
V
DD
= 3.3V, IOH = -12mA
2
V
Low-level Output Voltage
V
OL
V
DD
= 3.3V, IOL = 12mA
0.4
V
Input Capacitance
1
C
IN
V
IN
= V
DD
or GND
pF
1. Guaranteed by design, not 100% tested in production.
Operating Supply Current
Recommended Operating Conditions - SDRAM
SEL_DDR=0, SDRAM Outputs, V
DD3.3_2.5
= 3.3V, T
A
= 0 - 85
o
C (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD3.3_2.5
3
3.3
3.6
V
DD2.5
2.5
2.5
2.7
Input High Voltage
V
IH
SEL_DDR, PD# inputs
2
V
Input Low Voltage
V
IL
SEL_DDR, PD# inputs
0.8
V
Input Voltage Level
V
IN
V
Power Supply Voltage
V
5
ICS93738
0689A--01/09/03
Electrical Characteristics - Input / Supply / Common Output Parameters - DDR
SEL_DDR=1, DDR/DDR_SDRAM Outputs, V
DD3.3_2.5
= 2.5V, T
A
= 0 - 85
o
C (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Current
I
IH
V
IN
= V
DD
or GND
10
A
Input Low Current
I
IL
V
IN
= V
DD
or GND
-100
A
I
DD3.3_2.5
C
L
= 0 pF at 133 MHz
125
200
mA
I
DD2.5
C
L
= 0 pF at 133 MHz
90
200
mA
I
DDPD
C
L
= 0 pF
0
10
A
Output High Current
I
OH
V
DD
= 2.5V, V
OUT
= 1V
-18
mA
Output High Current
I
OL
V
DD
= 2.5V, V
OUT
= 1.2V
26
mA
High-level Output Voltage
V
OH
V
DD
= 2.5V, IOH = -12mA
1.7
V
Low-level Output Voltage
V
OL
V
DD
= 2.5V, IOL = 12mA
0.46
V
Output differential-pair
crossing voltage
1
C
IN
V
DD
/2 -
0.1
1.2
V
DD
/2 +
0.1
V
Input Capacitance
1
C
IN
V
IN
= V
DD
or GND
pF
1. Guaranteed by design, not 100% tested in production.
Operating Supply Current
Recommended Operating Conditions - DDR
SEL_DDR=1, DDR/DDR_SDRAM Outputs, V
DD3.3_2.5
= 2.5V, T
A
= 0 - 85
o
C (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD3.3_2.5
2.3
2.5
2.7
V
DD2.5
2.5
2.5
2.7
Input High Voltage
V
IH
SEL_DDR, PD# inputs
2
V
Input Low Voltage
V
IL
SEL_DDR, PD# inputs
0.8
V
Input Voltage Level
V
IN
V
Power Supply Voltage
V
6
ICS93738
0689A--01/09/03
Switching Waveforms
Duty Cycle Timing
SDRAM Buffer LH and HL Propagation Delay
INPUT
1.5V
1.5V
1.5V
1.5V
OUTPUT
t
6
t
7
t
1
t
2
1.5V
1.5V
1.5V
Switching Characteristics
T
A
= 0 - 85
o
C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Frequency
66
133
200
MHz
Input clock duty cycle
d
tin
40
50
60
%
Output to output Skew
1
(DDR outputs)
Output to output Skew
1
(SDRAM outputs)
Duty Cycle
1,3
V
T
= 50%, 66 MHz to 100 MHz , w/loads
48
49
52
(DDR outputs)
V
T
= 50%, 101 MHz to 167 MHz, w/loads
47
50
53
Duty Cycle
1,3
(SDRAM outputs)
Single-ended 20 - 80 %
133 MHz, Load = 120
/ 12 pF
Single-ended V
OL
= 0.4V, V
OH
= 2.4V
133 MHz, Load = 12 pF
1. Guaranteed by design, not 100% tested in production.
2. Refers to transistion on non-inverting output.
3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.
This is due to the formula: duty cycle = t2 / t1, where the cycle time (t1) decreases as the frequency increases.
ps
70
100
ps
80
150
V
T
= 1.5V, w/loads
T
skewDDR
T
skewSD
V
T
= 50%, Not including FB_OUT to outputs
V
T
= 1.5V
1.5
1.7
ns
Rise Time, Fall Time
1
(DDR
outputs)
950
DC
DDR
%
DC
SD
%
45
50
55
ps
t
rd
, t
fd
600
800
SDRAM Buffer LH
Propagation Delay
1,2
t
PLH
2
Rise Time, Fall Time
1
(SDRAM outputs)
t
rs
, t
fs
0.5
SDRAM Buffer HL
Propagation Delay
1,2
t
PHL
1.9
2.5
ns
Input edge greater than 1V/ns
Input edge greater than 1V/ns
2.5
ns
7
ICS93738
0689A--01/09/03
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches
for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop
after any complete byte has been transferred. The Command code and Byte count shown above must be
sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D4
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 7
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D5
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 7
Stop Bit
How to Read:
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D4
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 6
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D5
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 7
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
8
ICS93738
0689A--01/09/03
Ordering Information
ICS93738yFT
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - T
300 mil SSOP
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.03
10.68
.395
.420
E1
7.40
7.60
.291
.299
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
0
8
0
8
VARIATIONS
MIN
MAX
MIN
MAX
48
15.75
16.00
.620
.630
10-0034
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP
N
SEE VARIATIONS
SEE VARIATIONS
D mm.
D (inch)
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
0.635 BASIC
0.025 BASIC
COMMON DIMENSIONS
In Millimeters
In Inches
COMMON DIMENSIONS
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
h x 45
h x 45
E1
E
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
- C -
b
.10 (.004) C
.10 (.004) C
c
L
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