Integrated
Circuit
Systems, Inc.
ICS94201
94201 Rev A - 05/24/01
Pin Configuration
Recommended Application:
810/810E and Solano (815) type chipset
Output Features:
2 - CPUs @ 2.5V
13 - SDRAM @ 3.3V
3 - 3V66 @ 3.3V
8 - PCI @3.3V
1 - 24/48MHz@ 3.3V
1 - 48MHz @ 3.3V fixed
1 - REF @3.3V, 14.318MHz
Features:
Programmable ouput frequency.
Programmable ouput rise/fall time for PCI
and SDRAM clocks.
Programmable 3V66 to PCI skew.
Spread spectrum for EMI control
with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Support power management through PD#.
Uses external 14.318MHz crystal.
FS pins for frequency select
Key Specifications:
CPU Output Jitter: <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
CPU Output Skew: <175ps
PCI Output Skew: <500ps
3V66 Output Skew <175ps
For group skew timing, please refer to the
Group Timing Relationship Table.
Programmable System Frequency Generator for P
II
/
III
TM
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK [1:0]
2
12
8
3
SDRAM [11:0]
IOAPIC
PCICLK [7:0]
SDRAM_F
3V66 [2:0]
X1
X2
XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
FS[4:0]
PD#
SEL24_48#
SDATA
SCLK
Control
Logic
Config.
Reg.
/ 2
REF0
Block Diagram
VDDREF
X1
X2
GNDREF
GND3V66
3V66-1
3V66-2
VDD3V66
VDDPCI
*(FS0)PCICLK0
*(FS1)PCICLK1
*(SEL24_48#)PCICLK2
GNDPCI
PCICLK3
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PD#
SCLK
SDATA
VDDSDR
SDRAM11
SDRAM10
GNDSDR
3V66-0
1
1
1
REF0(FS4)*
VDDLAPIC
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
24_48MHz(FS2)*
48MHz(FS3)*
VDD48
VDDSDR
SDRAM8
SDRAM9
GNDSDR
1
1
ICS94201
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS94201
General Description
Pin Configuration
The ICS94201 is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It provides all necessary
clock signals for such a system.
The ICS94201 belongs to ICS new generation of programmable system clock generators. It employs serial programming I
2
C interface
as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew,
changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over
clocking.
Spread spectrum typically reduces system EMI by 7dB to 8dB. This simplifies EMI qualification without resorting to board design
iterations or costly shielding.
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3
ICS94201
General I
2
C serial interface information for the ICS94201
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending Byte 0 through Byte 28
(see Note 2)
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends Byte 0 through byte 6 (default)
ICS clock sends Byte 0 through byte X (if X
(H)
was
written to byte 6).
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 26
ACK
Byte 27
ACK
Byte 28
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
If 7
H
has been written to B6
Byte 7
ACK
If 1A
H
has been written to B6
Byte26
ACK
If 1B
H
has been written to B6
Byte 27
ACK
If 1C
H
has been written to B6
Byte 28
ACK
Stop Bit
How to Read:
*See notes on the following page
.
4
ICS94201
Notes:
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Readback will support standard SMBUS controller protocol. The number of bytes to read back is defined
by writing to byte 6.
2.
When writing to bytes 14 - 15, bytes 16 - 17 and bytes 18 - 20, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4.
The input is operating at 3.3V logic levels.
5.
The data byte format is 8-bit bytes.
6.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
Register Name
Byte
Description
Pwd Default
Functionality & Frequency Select
Register
0
Output frequency, hardware / I
2
C frequency
select, spread spectrum & output enable
control register.
See individual byte
des cription
Output Control Registers
1-5
Active / inactive output control registers.
See individual byte
des cription
Byte Count Read Back Register
6
W riting to this register will configure byte
count and how many byte will be read back.
Do not write 00
H
to this byte.
06
H
Latched Inputs Read Back
Register
7
The inverse of the latched inputs level could
be read back from this register.
See individual byte
des cription
W atchdog Control Registers
8 Bit[6:0]
W atchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
000,0000
VCO Control Selection Bit
8 Bit[7]
This bit selects whether the output
frequency is controled by hardware/byte 0
configurations or byte 14&15 programming.
0
W atchdog Timer Count Register
9
W riting to this register will configure the
number of seconds for the watchdog timer
to reset.
FF
H
ICS Reserved Register
10
This is an unused register. W riting to this
register will not affect device functionality.
00
H
Device ID, Vendor ID & Revision ID
Registers
11-12
Byte 11 bit[3:0] is ICS vendor id - 0001.
Other bits in these 2 registers designate
device revision ID of this part.
See individual byte
des cription
ICS Reserved Register
13
Don't write into this register, writing 1's will
cause malfunction.
00
H
VCO Frequency Control Registers
14-15
These registers control the dividers ratio
into the phase detector and thus control the
VCO output frequency.
Depend on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
16-17
These registers control the spread
percentage amount.
Depend on
hardware/byte 0
configuration
Output Dividers Control Registers
18-20
Changing bits in these registers result in
frequency divider ratio changes. Incorrect
configuration of group output divider ratio
can cause system malfunction.
Depend on
hardware/byte 0
configuration
Group Skews Control Registers
21-23
Increment or decrement the group skew
amount as compared to the initial skew.
See individual byte
des cription
Output Rise/Fall Time Select
Registers
24
These registers will control the group rise
and fall time.
See individual byte
des cription
Brief I
2
C registers description for ICS94201
Programmable System Frequency Generator
5
ICS94201
Byte 0: Functionality and frequency select register (Default=0)
Notes:
1.
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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6
ICS94201
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Byte 5: Output Control Register
(1 = enable, 0 = disable)
Byte 6: Byte Count Read Back Register
Note: Writing to this register will configure byte count and
how many bytes will be read back, default is 6 bytes.
t
i
B
#
n
i
P
D
W
P
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o
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t
p
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D
7
t
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9
3
1
7
M
A
R
D
S
6
t
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B
0
4
1
6
M
A
R
D
S
5
t
i
B
2
4
1
5
M
A
R
D
S
4
t
i
B
3
4
1
4
M
A
R
D
S
3
t
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B
4
4
1
3
M
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R
D
S
2
t
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6
4
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2
M
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1
t
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B
7
4
1
1
M
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0
t
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8
4
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0
M
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t
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#
n
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D
7
t
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8
1
2
_
6
6
V
3
6
t
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B
6
1
0
_
6
6
V
3
5
t
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B
7
1
1
_
6
6
V
3
4
t
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B
-
X
#
4
S
F
3
t
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B
4
5
1
C
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2
t
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B
-
X
#
1
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1
t
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1
5
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1
K
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2
5
1
0
K
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t
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P
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p
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D
7
t
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0
)
e
t
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N
(
d
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v
r
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R
6
t
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-
0
)
e
t
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N
(
d
e
v
r
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s
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R
5
t
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B
-
0
)
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t
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N
(
d
e
v
r
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s
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R
4
t
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B
-
0
)
e
t
o
N
(
d
e
v
r
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s
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R
3
t
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B
-
0
)
e
t
o
N
(
d
e
v
r
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s
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R
2
t
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B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
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s
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R
0
t
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B
-
0
)
e
t
o
N
(
d
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s
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R
t
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B
#
n
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P
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7
t
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-
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d
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v
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R
(
6
t
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-
1
)
d
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v
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R
(
5
t
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B
-
1
)
d
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v
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R
(
4
t
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B
-
1
)
d
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R
(
3
t
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6
2
1
1
1
M
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2
t
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B
7
2
1
0
1
M
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S
1
t
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0
3
1
9
M
A
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D
S
0
t
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B
1
3
1
8
M
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D
S
t
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#
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P
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D
7
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0
2
1
7
K
L
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P
6
t
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9
1
1
6
K
L
C
I
C
P
5
t
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B
7
1
1
5
K
L
C
I
C
P
4
t
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B
6
1
1
4
K
L
C
I
C
P
3
t
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5
1
1
3
K
L
C
I
C
P
2
t
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3
1
1
2
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1
t
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2
1
1
1
K
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0
t
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1
1
1
0
K
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t
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#
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7
t
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-
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#
3
S
F
6
t
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-
X
#
0
S
F
5
t
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B
-
X
#
2
S
F
4
t
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5
3
1
z
H
M
4
2
3
t
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-
1
)
d
e
v
r
e
s
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R
(
2
t
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4
3
1
z
H
M
8
4
1
t
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-
1
)
d
e
v
r
e
s
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R
(
0
t
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B
8
3
1
F
_
M
A
R
D
S
7
ICS94201
Byte 7: Latch Inputs Readback Register
Byte 9: Watchdog Timer Count Register
Byte 8: VCO Control Selection Bit &
Watchdog Timer Control Register
Byte 10: ICS Reserved Register
Byte 11: Vender ID & Device ID Register
Byte 12: Revision ID Register
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000 entry in
byte0.
Note: This is an unused register. Writing to this register will
not affect device performance or functionality.
Note: ICS Vendor ID is 0001 as in Number 1 in
frequency generation.
Notes:
1. PWD = Power on Default
t
i
B
D
W
P
n
o
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t
p
i
r
c
s
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D
7
t
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B
0
q
e
r
f
5
1
&
4
1
B
=
1
/
q
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r
f
0
B
/
w
H
=
0
6
t
i
B
0
e
l
b
a
n
e
=
1
/
e
l
b
a
s
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d
=
0
e
l
b
a
n
E
D
W
5
t
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B
0
m
r
a
l
a
=
1
/
l
a
m
r
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n
=
0
s
u
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W
4
t
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4
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F
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3
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Note: Device ID and Revision ID values will be based on
individual device and its revision.
8
ICS94201
Byte 13: ICS Reserved Register
Byte 15: VCO Frequency Control Register
Note: The decimal representation of these 9 bits (Byte 15 bit
[7:0] & Byte 14 bit [7] ) + 8 is equal to the VCO divider value.
For example if VCO divider value of 36 is desired, user need
to program 36 - 8 = 28, namely, 0, 00011100 into byte 15 bit
& byte 14 bit 7.
Note: DON'T write a '1' into this register, it will
cause malfunction.
Byte 14: VCO Frequency Control Register
Note: The decimal representation of these 7 bits (Byte 14
[6:0]) + 2 is equal to the REF divider value .
To program the VCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming.
1. Select the frequency you want to over-clock from with the desired gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by writing to
byte 0, or using initial hardware power up frequency.
2. Write 0001, 1001 (19
H
) to byte 6 for readback of 25 bytes (byte 0-24).
3. Read back byte 16-24 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 8 bit 7 indicating you want to use byte 14 and 15 to control the VCO frequency.
6. Write to byte 14 & 15 with the desired VCO & REF divider values.
7. Write to byte 16 to 24 with the values you copy from step 3. This maintains the output divider mux controls the same gear ratio.
8. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needs to be changed again,
user only needs to write to byte 14 and 15 unless the system is to reboot.
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)
-0.5
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9
ICS94201
Byte 16: Spread Sectrum Control Register
Byte 17: Spread Spectrum Control Register
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Byte 18: Output Dividers Control Register
Byte 19: Output Dividers Control Register
Note: Changing bits in these registers results in frequency
divider ratio changes. Incorrect configuration of
group gear ratio can cause system malfunction.
Note: Changing bits in these registers results in frequency
divider ratio changes. Incorrect configuration of
group gear ratio can cause system malfunction.
Notes:
1. PWD = Power on Default
2. The power on default for byte 16-20 depends on the harware (latch inputs FS[0:4]) or IIC (Byte 0 bit [1:7]) setting. Be sure to read
back and re-write the values of these 5 registers when VCO frequency change is desired for the first pass.
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Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with the wrong spread percentage and/or group to group divider ratio
programmed into bytes 16-20 could be unstable. Step 3 & 7 assure the correct spread and gear ratio.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow.
Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4. Users can also utilize software utility provided to program the VCO frequency from ICS Application Engineering.
5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spread amount desired.
See Application note for software support.
10
ICS94201
Byte 21: ICS Reserved Register
Byte 23: Group Skew Control Register
Byte 22: Group Skew Control Register
Note: Default 3V66 to PCI skew is 2.5ns bit [7:4]=1001.
Each increment or decrement of bit 4 to 7 will
introduce 100ps delay or advance on all PCI
clocks.
Byte 24: Output Rise/Fall Time Select Register
Note: This is an unused register. Writing to this register will
not affect device performance or functionality.
Byte 20: Output Dividers Control Register
Note: Changing bits in these registers results in
frequency divider ratio changes. Incorrect
configuration of group gear ratio can cause
system malfunction.
Notes:
1. PWD = Power on Default
2. The power on default for byte 16-20 depends on the hardware
(latch inputs FS[0:4]) or I
2
C (Byte 0 bit [1:7]) setting. Be sure
to read back and re-write the values of these 5 registers when
VCO frequency change is desired for the first pass.
3. If Byte 8 bit 7 is driven to "1" meaning programming is
intended, Byte 21-24 will lose their default power up value.
Note: Default 3V66 to IOAPIC skew is 2.5ns bit [3:0]=0111.
Each increment or decrement of bit 4 to 7 will introduce
100ps delay or advance on all IOAPIC clocks.
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
3
2
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
6
t
i
B
X
2
2
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
5
t
i
B
X
1
2
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
4
t
i
B
X
0
2
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
3
t
i
B
X
9
1
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
2
t
i
B
X
8
1
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
1
t
i
B
X
7
1
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
0
t
i
B
X
6
1
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
)
d
e
v
r
e
s
e
R
(
6
t
i
B
0
)
d
e
v
r
e
s
e
R
(
5
t
i
B
0
)
d
e
v
r
e
s
e
R
(
4
t
i
B
0
)
d
e
v
r
e
s
e
R
(
3
t
i
B
0
)
d
e
v
r
e
s
e
R
(
2
t
i
B
0
)
d
e
v
r
e
s
e
R
(
1
t
i
B
0
)
d
e
v
r
e
s
e
R
(
0
t
i
B
0
)
d
e
v
r
e
s
e
R
(
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
1
3
t
i
B
w
e
k
S
I
C
P
o
t
6
6
V
3
6
t
i
B
0
2
t
i
B
w
e
k
S
I
C
P
o
t
6
6
V
3
5
t
i
B
0
1
t
i
B
w
e
k
S
I
C
P
o
t
6
6
V
3
4
t
i
B
1
0
t
i
B
w
e
k
S
I
C
P
o
t
6
6
V
3
3
t
i
B
0
)
d
e
v
r
e
s
e
R
(
2
t
i
B
0
)
d
e
v
r
e
s
e
R
(
1
t
i
B
0
)
d
e
v
r
e
s
e
R
(
0
t
i
B
0
)
d
e
v
r
e
s
e
R
(
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
)
d
e
v
r
e
s
e
R
(
6
t
i
B
0
k
a
e
W
=
1
,
l
a
m
r
o
N
=
0
F
E
R
5
t
i
B
0
k
a
e
W
=
1
,
l
a
m
r
o
N
=
0
z
h
M
8
4
,
4
2
4
t
i
B
0
)
d
e
v
r
e
s
e
R
(
3
t
i
B
0
k
a
e
W
=
1
,
l
a
m
r
o
N
=
0
I
C
P
2
t
i
B
0
k
a
e
W
=
1
,
l
a
m
r
o
N
=
0
6
6
V
3
1
t
i
B
0
k
a
e
W
=
1
,
l
a
m
r
o
N
=
0
M
A
R
D
S
0
t
i
B
0
)
d
e
v
r
e
s
e
R
(
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
)
d
e
v
r
e
s
e
R
(
6
t
i
B
0
)
d
e
v
r
e
s
e
R
(
5
t
i
B
0
)
d
e
v
r
e
s
e
R
(
4
t
i
B
0
)
d
e
v
r
e
s
e
R
(
3
t
i
B
0
3
t
i
B
w
e
k
S
C
I
P
A
O
I
o
t
6
6
V
3
2
t
i
B
1
2
t
i
B
w
e
k
S
C
I
P
A
O
I
o
t
6
6
V
3
1
t
i
B
1
1
t
i
B
w
e
k
S
C
I
P
A
O
I
o
t
6
6
V
3
0
t
i
B
1
0
t
i
B
w
e
k
S
C
I
P
A
O
I
o
t
6
6
V
3
11
ICS94201
Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . 0C to +70C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115C
Group Timing Relationship Table
1
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+0.3
V
Input Low Voltage
V
IL
V
SS
-0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
-5
5
A
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
-5
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
C
L
= max cap loads;
CPU=66-133 MHz, SDRAM=100 MHz
334
350
CPU=133 MHz, SDRAM=133 MHz
465
500
I
DD2.5OP
C
L
= max cap loads;
20
70
Powerdown Current
I
DD3.3PD
C
L
= 0 pF; Input address to VDD or GND
280
600
A
Input Frequency
F
i
V
DD
= 3.3 V
14.318
MHz
Pin Inductance
L
pin
7
nH
C
IN
Logic Inputs
5
pF
C
OUT
Output pin capacitance
6
pF
C
INX
X1 & X2 pins
27
45
pF
Transition time
1
T
trans
To 1st crossing of target frequency
3
ms
Settling time
1
T
s
From 1st crossing to 1% target frequency
3
ms
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target frequency
3
ms
t
PZH
,t
PZL
Output enable delay (all outputs)
1
10
ns
t
PHZ
,t
PLZ
Output disable delay (all outputs)
1
10
ns
1
Guaranteed by design, not 100% tested in production.
Delay
1
Input Capacitance
1
Input Low Current
A
I
DD3.3OP
Operating Supply
Current
mA
Offset
Tolerance
Offset
Tolerance
Offset
Tolerance
Offset
Tolerance
CPU to SDRAM
2.5 ns
500 ps
5.0 ns
500 ps
0.0 ns
500 ps
3.75 ns
500 ps
CPU to 3V66
7.5 ns
500 ps
5.0 ns
500 ps
0.0 ns
500 ps
0.0 ns
500 ps
SDRAM to 3V66
0.0 ns
500 ps
0.0 ns
500 ps
0.0 ns
500 ps
3.75 ns
500 ps
3V66 to PCI
1.5-3.5ns
500 ps
1.5-3.5ns
500 ps
1.5-3.5ns
500 ps
1.5-3.5ns
500 ps
PCI to IOAPIC
0.0 ns
1.0 ns
0.0 ns
1.0 ns
0.0 ns
1.0 ns
0.0 ns
1.0 ns
USB & DOT
Asynch
N/A
Asynch
N/A
Asynch
N/A
Asynch
N/A
1
Guaranteed by design, not 100% tested in production.
Group
SDRAM 100 MHz
SDRAM 100 MHz
SDRAM 100 MHz
SDRAM 133 MHz
CPU 66 MHz
CPU 100 MHz
CPU 133 MHz
CPU 133 MHz
12
ICS94201
Electrical Characteristics - CPU
T
A
= 0 - 70 C; V
DDL
= 2.5 V +/-5%; C
L
= 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
1
R
DSP2B
Vo=V
DD
*(0.5)
13.5
15
45
Output Impedance
1
R
DSN2B
Vo=V
DD
*(0.5)
13.5
16.5
45
Output High Voltage
V
OH2B
I
OH
= -1 mA
2
2.48
V
Output Low Voltage
V
OL2B
I
OL
= 1 mA
0.04
0.4
V
V
OH@MIN
= 1 V
-60
-27
V
OH@MAX
= 2.375V
-27
-7
V
OL@MIN
= 1.2 V
27
63
V
OL@MAX
=0.3V
20
30
Rise Time
1
t
r2B
V
OL
= 0.4 V, V
OH
= 2.0 V
0.4
1
1.6
ns
Fall Time
1
t
f2B
V
OH
= 2.0 V, V
OL
= 0.4 V
0.4
1
1.6
ns
Duty Cycle
1
d
t2B
V
T
= 1.25 V
45
50
55
%
Skew
1
t
sk2B
V
T
= 1.25 V
30
175
ps
V
T
= 1.25 V, CPU 66, SDRAM 100
300
350
CPU 100, SDRAM 100
240
250
CPU 133, SDRAM 100
400
500
CPU 133, SDRAM 133
300
350
1
Guaranteed by design, not 100% tested in production.
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
ps
mA
mA
Output High Current
I
OH2B
Output Low Current
I
OL2B
Electrical Characteristics - 3V66
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
1
R
DSP1
V
O
= V
DD
*(0.5)
12
55
Output Impedance
1
R
DSN1
V
O
= V
DD
*(0.5)
12
55
Output High Voltage
V
OH1
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= 1 mA
0.55
V
V
OH @ MIN
= 1.0 V
-33
V
OH @ MAX
= 3.135 V
-33
V
OL @ MIN
= 1.95 V
30
V
OL @ MAX
= 0.4 V
38
Rise Time
1
t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V
0.4
1
1.6
ns
Fall Time
1
t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V
0.4
0.9
1.6
ns
Duty Cycle
1
d
t1
V
T
= 1.5 V
45
49
55
%
Skew
1
t
sk1
V
T
= 1.5 V
35
175
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc1
V
T
= 1.5 V
220
500
ps
1
Guaranteed by design, not 100% tested in production.
Output High Current
Output Low Current
mA
mA
I
OH1
I
OL1
13
ICS94201
Electrical Characteristics - IOAPIC
T
A
= 0 - 70 C; V
DDL
= 2.5 V +/-5%; C
L
= 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
1
R
DSP4B
Vo=V
DD
*(0.5)
9
3
Output Impedance
1
R
DSN4B
Vo=V
DD
*(0.5)
9
30
Output High Voltage
V
OH4B
I
OH
= -5.5 mA
2
V
Output Low Voltage
V
OL4B
I
OL
= 9 mA
0.4
V
V
OH@MIN
= 1.4 V
-21
V
OH@MAX
= 2.5V
-36
V
OL@MIN
= 1.0 V
36
V
OL@MAX
=0.2V
31
Rise Time
1
t
r4B
V
OL
= 0.4 V, V
OH
= 2.0 V
0.4
1.2
1.6
ns
Fall Time
1
t
f4B
V
OH
= 2.0 V, V
OL
= 0.4 V
0.4
1.1
1.6
ns
Duty Cycle
1
d
t4B
V
T
= 1.25 V
45
50
55
%
Jitter, Cycle-to-cycle
1
t
jcyc-cyc4B
V
T
= 1.25 V
240
500
ps
1
Guaranteed by design, not 100% tested in production.
mA
mA
Output High Current
I
OH4B
Output Low Current
I
OL4B
Electrical Characteristics - SDRAM
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%, C
L
= 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
1
R
DSP3
Vo=V
DD
*(0.5)
10
24
Output Impedance
1
R
DSN3
Vo=V
DD
*(0.5)
10
24
Output High Voltage
V
OH3
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL3
I
OL
= 1 mA
0.4
V
V
OH@MIN
= 2 V
-46
V
OH@MAX
= 3.135V
-54
V
OL@MIN
= 1 V
54
V
OL@MAX
=0.4V
53
Rise Time
1
t
r3
V
OL
= 0.4 V, V
OH
= 2.4 V
0.4
0.9
1.6
ns
Fall Time
1
t
f3
V
OH
= 2.4 V, V
OL
= 0.4 V
0.4
0.8
1.6
ns
Duty Cycle
1
d
t3
V
T
= 1.5 V
45
49
55
%
Skew
1
t
sk3
V
T
= 1.5 V
100
250
ps
Jitter, cycle-to-cycle
1
t
jcyc-cyc3
V
T
= 1.5 V
350
500
ps
1
Guaranteed by design, not 100% tested in production.
mA
mA
Output High Current
I
OH3
Output Low Current
I
OL3
14
ICS94201
Electrical Characteristics - PCI
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%, C
L
= 40 pF for PCI0-1, C
L
= 10 - 30 pF for other PCIs (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
1
R
DSP1
Vo=V
DD
*(0.5)
12
55
Output Impedance
1
R
DSN1
Vo=V
DD
*(0.5)
12
55
Output High Voltage
V
OH1
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= 1 mA
0.55
V
V
OH@MIN
= 1 V
-33
V
OH@MAX
= 3.135V
-33
V
OL@MIN
= 1.95 V
30
V
OL@MAX
=0.4V
38
V
OL
= 0.4 V, V
OH
= 2.4 V, PCI0-3
1.8
2
PCI3-7
2.2
2.5
V
OL
= 2.4 V, V
OH
= 0.4 V, PCI0-3
1.8
2
PCI3-7
2.3
2.5
Duty Cycle
1
d
t1
V
T
= 1.5 V
45
51
55
%
Skew
1
t
sk1
V
T
= 1.5 V
150
500
ps
Jitter, cycle-to-cycle
1
t
jcyc-cyc1
V
T
= 1.5 V
200
500
ps
1
Guaranteed by design, not 100% tested in production.
mA
mA
Output High Current
I
OH1
Output Low Current
I
OL1
t
r1
Rise Time
1
Fall Time
1
t
f1
ns
ns
0.5
0.5
Electrical Characteristics - REF, 24_48MHz, 48MHz
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
1
R
DSP5
V
O
= V
DD
*(0.5)
20
60
Output Impedance
1
R
DSN5
V
O
= V
DD
*(0.5)
20
60
Output High Voltage
V
OH5
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL5
I
OL
= 1 mA
0.4
V
V
OH @ MIN
= 1.0 V
-23
V
OH @ MAX
= 3.135 V
-29
V
OL @ MIN
= 1.95 V
29
V
OL @ MAX
= 0.4 V
27
Rise Time
1
t
r5
V
OL
= 0.4 V, V
OH
= 2.4 V
0.4
2
4
ns
Fall Time
1
t
f5
V
OH
= 2.4 V, V
OL
= 0.4 V
0.4
2
4
ns
Duty Cycle
1
d
t5
V
T
= 1.5 V
45
53
55
%
V
T
= 1.5 V, Fixed clocks
200
500
V
T
= 1.5 V, Ref clocks
2300
3000
1
Guaranteed by design, not 100% tested in production.
Jitter, cycle-to-cycle
1
t
jcyc-cyc5
ps
Output High Current
I
OH5
mA
Output Low Current
I
OL5
mA
15
ICS94201
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS94201
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage) that
is present on these pins at this time is read and stored into a 5-
bit internal data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In this
mode the pins produce the specified buffered clocks to external
loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
W
8.2K
W
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
16
ICS94201
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the
output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
17
ICS94201
Group Offset Waveforms
Cycle Repeats
0ns
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 133MHz
SDRAM 100MHz
3.5V 66MHz
PCI 33MHz
APIC 33MHz
REF 14.318MHz
USB 48MHz
10ns
20ns
30ns
40ns
18
ICS94201
Ordering Information
ICS94201yFT
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - T
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
h x 45
h x 45
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
- C -
b
.10 (.004) C
.10 (.004) C
c
L
300 mil SSOP Package
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.03
10.68
.395
.420
E1
7.40
7.60
.291
.299
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
0
8
0
8
MIN
MAX
MIN
MAX
56
18.31
18.55
.720
.730
10-0034
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
SEE VARIATIONS
SEE VARIATIONS
0.635 BASIC
0.025 BASIC
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
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