ICS94208
Integrated
Circuit
Systems, Inc.
0613A--01/13/03
Programmable Frequency Generator & Integrated Buffers for K7 Processor
Block Diagram
Recommended Application:
Single chip clock solution for SIS 730S K7 chipset.
Output Features:
1 - Differential pair open drain CPU clock
1 - Single-ended open drain CPU clock
13 - SDRAM @ 3.3V
6- PCI @3.3V,
2 - AGP @ 3.3V
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I
2
C
(Default is 24MHz)
2- REF @3.3V, 14.318MHz.
Features:
Programmable ouput frequency.
Programmable ouput rise/fall time.
Programmable SDRAM and CPU skew.
Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
FS pins for frequency select
Functionality
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
VDDREF
(AGPSEL)REF0
*(FS3)REF1
GNDREF
X1
X2
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GNDPCI
VDDAGP
AGPCLK0
AGPCLK1
GNDAGP
GND48
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
1
1
*
VDDA
CPUCLKC0
CPUCLKT0
CPUCLKT1
GNDCPU
VDDSDR
SDRAM0
SDRAM1
SDRAM2
GNDSDR
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GNDSDR
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GNDSDR
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR
ICS94208
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLKC0
SDRAM (12:0)
PCICLK (4:0)
AGP (1:0)
CPUCLKT (1:0)
PCICLK_F
2
5
13
2
2
X1
X2
XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
PCI
DIVDER
Stop
Stop
Stop
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
AGP_SEL
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
AGP
DIVDER
0
0
0
0
100.00
100.00
33.33
66.67
50.00
0
0
0
1
100.00
133.33
33.33
66.67
50.00
0
0
1
0
100.00
150.00
30.00
60.00
50.00
0
0
1
1
100.00
66.67
33.33
66.67
50.00
0
1
0
0
112.00
112.00
33.60
67.20
56.00
0
1
0
1
125.00
100.00
31.25
62.50
50.00
0
1
1
0
124.00
124.00
31.00
62.00
46.50
0
1
1
1
133.33
100.00
33.33
66.67
50.00
1
0
0
0
133.33
133.33
33.33
66.67
50.00
1
0
0
1
150.00
150.00
30.00
60.00
50.00
1
0
1
0
111.11
166.67
33.33
66.67
55.56
1
0
1
1
110.00
165.00
33.00
66.00
55.00
1
1
0
0
166.67
166.67
33.33
66.67
55.56
1
1
0
1
90.00
90.00
30.00
60.00
45.00
1
1
1
0
48.00
48.00
32.00
64.00
48.00
1
1
1
1
45.00
60.00
30.00
60.00
45.00
PCICLK
FS3 FS2 FS1 FS0
CPU
SDRAM
AGP
SEL = 0
AGP
SEL = 1
2
ICS94208
0613A--01/13/03
The ICS94208 is a single chip clock solution for desktop
designs using SIS 730S K7 style chipset. It provides all
necessary clock signals for such a system.
The ICS94208 belongs to ICS new generation of
programmable system clock generators. It employs serial
programming I
2
C interface as a vehicle for changing
output functions, changing output frequency, configuring
output strength, configuring output to output skew, changing
spread spectrum amount, changing group divider ratio and
dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system become unstable
from over clocking.
General Description
Power Groups
VDDREF = REF, X1, X2
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDD48 = 48MHz, 24MHz, fixed PLL
VDDA = Core, PLL
VDDAGP=AGP
Pin Configuration
E
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#
D
P
MODE Pin Power Management Control Input
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 7, 15, 22, 25,
35, 43
VDD
PWR
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
AGPSEL
IN
AGP frequency select pin.
REF0
OUT
14.318 MHz reference clock.
FS3
IN
Frequency select pin.
REF1
OUT
14.318 MHz reference clock.
4, 14, 18, 19, 29,
32, 39, 44
GND
PWR
Ground pin for 3V outputs.
5
X1
IN
Crystal input,nominally 14.318MHz.
6
X2
OUT
Crystal output, nominally 14.318MHz.
FS1
IN
Frequency select pin.
PCICLK_F
OUT
PCI clock output, not affected by PCI_STOP#
FS2
IN
Frequency select pin.
PCICLK0
OUT
PCI clock output.
10, 11, 12, 13
PCICLK [1:4]
OUT
PCI clock outputs.
17, 16
AGP (1:0)
OUT
AGP outputs defined as 2X PCI. These may not be stopped.
FS0
IN
Frequency select pin.
48MHz
OUT
48MHz output clock
MODE
IN
Pin 27, 28, 30, & 31 function select pin
0=Desktop 1=Mobile mode
24_48MHz
OUT
Clock output for super I/O/USB default is 24MHz
23
SDATA
I/O
Data pin for I
2
C circuitry 5V tolerant
24
SCLK
IN
Clock input of I2C input, 5V tolerant input
CPU_STOP#
IN
Stops all CPU clocks at logic 0 level, when input low
SDRAM11
OUT
SDRAM clock output
PCI_STOP#
IN
Stops all PCI clocks at logic 0 level, when input low, except
PCICLK_F which is free running
SDRAM9
OUT
SDRAM clock output
SDRAM_STOP#
IN
Stops all SDRAM clocks at logic 0 level, when input low
SDRAM9
OUT
SDRAM clock output
PD#
IN
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms.
SDRAM8
OUT
SDRAM clock output
26, 33, 34, 36,
37, 38, 40, 41,
42
SDRAM (12,
7:0)
OUT
SDRAM clock outputs
47
CPUCLKC0
OUT
"Complementary" clocks of differential pair CPU outputs. These
open drain outputs need an external 1.5V pull-up.
45, 46
CPUCLKT (1:0)
OUT
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
48
VDDA
PWR
3.3V Power pin for core, PLL
31
20
2
8
9
21
3
30
28
27
3
ICS94208
0613A--01/13/03
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: PWD = Power-Up Default
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
I
2
C is a trademark of Philips Corporation
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3
3
.
3
3
7
6
.
6
6
0
0
.
0
5
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
1
1
1
5
2
.
4
0
1
0
0
.
9
3
1
5
7
.
4
3
0
5
.
9
6
3
1
.
2
5
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
3
t
i
B
s
t
u
p
n
I
d
e
h
c
t
a
L
,
t
c
e
l
e
s
e
r
a
w
d
r
a
h
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
0
4
:
7
2
,
t
i
B
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
1
0
1
t
i
B
l
a
m
r
o
N
-
0
d
e
l
b
a
n
E
m
u
r
t
c
e
p
S
d
a
e
r
p
S
-
1
0
0
t
i
B
g
n
i
n
n
u
R
-
0
s
t
u
p
t
u
o
ll
a
e
t
a
t
s
i
r
T
-
1
0
4
ICS94208
0613A--01/13/03
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
3
1
1
4
K
L
C
I
C
P
4
t
i
B
2
1
1
3
K
L
C
I
C
P
3
t
i
B
1
1
1
2
K
L
C
I
C
P
2
t
i
B
0
1
1
1
K
L
C
I
C
P
1
t
i
B
9
1
0
K
L
C
I
C
P
0
t
i
B
8
1
F
_
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are
disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted
logic
load of the input frequency select pin conditions.
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
1
2
1
z
H
M
8
4
_
4
2
5
t
i
B
0
2
1
z
H
M
8
4
4
t
i
B
6
2
1
2
1
M
A
R
D
S
3
t
i
B
7
2
1
1
1
M
A
R
D
S
2
t
i
B
8
2
1
0
1
M
A
R
D
S
1
t
i
B
0
3
1
9
M
A
R
D
S
0
t
i
B
1
3
1
8
M
A
R
D
S
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
3
S
F
6
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
2
S
F
5
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
1
S
F
4
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
0
S
F
3
t
i
B
2
1
0
F
E
R
2
t
i
B
3
1
1
F
E
R
1
t
i
B
7
1
1
1
K
L
C
P
G
A
0
t
i
B
6
1
1
0
K
L
C
P
G
A
Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
3
3
1
7
M
A
R
D
S
6
t
i
B
4
3
1
6
M
A
R
D
S
5
t
i
B
6
3
1
5
M
A
R
D
S
4
t
i
B
7
3
1
4
M
A
R
D
S
3
t
i
B
8
3
1
3
M
A
R
D
S
2
t
i
B
0
4
1
2
M
A
R
D
S
1
t
i
B
1
4
1
1
M
A
R
D
S
0
t
i
B
2
4
1
0
M
A
R
D
S
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
8
4
_
4
2
l
e
S
)
z
H
M
8
4
:
0
,
z
H
M
4
2
:
1
(
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
7
4
1
0
C
K
L
C
U
P
C
2
t
i
B
6
4
1
0
T
K
L
C
U
P
C
1
t
i
B
5
4
1
1
T
K
L
C
U
P
C
0
t
i
B
-
1
d
e
v
r
e
s
e
R
5
ICS94208
0613A--01/13/03
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
d
e
v
r
e
s
e
R
6
t
i
B
-
0
d
e
v
r
e
s
e
R
5
t
i
B
-
0
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
0
d
e
v
r
e
s
e
R
2
t
i
B
-
0
d
e
v
r
e
s
e
R
1
t
i
B
-
0
d
e
v
r
e
s
e
R
0
t
i
B
-
0
d
e
v
r
e
s
e
R
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
3
,
2
0
X
2
=
1
,
X
1
=
0
h
t
g
n
e
r
t
s
F
E
R
6
t
i
B
5
4
0
l
o
r
t
n
o
C
-
p
o
t
S
-
1
C
K
L
C
U
P
C
,
1
C
K
L
C
U
P
C
l
o
r
t
n
o
c
l
l
i
w
#
P
O
T
S
_
U
P
C
=
0
w
o
l
s
i
#
P
O
T
S
_
U
P
C
f
i
n
e
v
e
g
n
i
n
n
u
r
e
e
r
f
s
i
1
C
K
L
C
U
P
C
=
1
5
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
L
E
S
P
G
A
4
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
E
D
O
M
3
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
#
P
O
T
S
_
U
P
C
2
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
#
P
O
T
S
_
I
C
P
1
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
#
P
O
T
S
_
M
A
R
D
S
0
t
i
B
-
0
e
l
g
g
o
T
d
e
e
p
S
P
G
A
,
g
n
i
t
t
e
s
t
u
p
n
i
h
c
t
a
l
y
b
d
e
n
i
m
r
e
t
e
d
e
b
l
l
i
w
)
2
n
i
p
(
L
E
S
P
G
A
=
0
g
n
i
t
t
e
s
t
u
p
n
i
h
c
t
a
l
f
o
e
t
i
s
o
p
p
o
e
b
l
l
i
w
L
E
S
P
G
A
=
1
Byte 8: Byte Count and Read Back Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
d
e
v
r
e
s
e
R
6
t
i
B
-
0
d
e
v
r
e
s
e
R
5
t
i
B
-
0
d
e
v
r
e
s
e
R
4
t
i
B
-
0
d
e
v
r
e
s
e
R
3
t
i
B
-
0
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
0
d
e
v
r
e
s
e
R
0
t
i
B
-
0
d
e
v
r
e
s
e
R
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
q
e
r
f
5
1
&
4
1
B
=
1
/
q
e
r
f
0
B
/
w
H
=
0
6
t
i
B
0
e
l
b
a
n
e
=
1
/
e
l
b
a
s
i
d
=
0
e
l
b
a
n
E
D
W
5
t
i
B
0
m
r
a
l
a
=
1
/
l
a
m
r
o
n
=
0
s
u
t
a
t
S
D
W
4
t
i
B
0
2
t
i
b
0
e
t
y
B
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
3
t
i
B
0
3
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
2
t
i
B
0
2
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
1
t
i
B
0
1
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
0
t
i
B
0
0
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
Byte 9: Watchdog Timer Count Register
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
e
s
e
h
t
f
o
n
o
i
t
a
t
n
e
s
e
r
p
e
r
l
a
m
i
c
e
d
e
h
T
s
m
1
r
o
s
m
0
9
2
o
t
d
n
o
p
s
e
r
r
o
c
s
t
i
b
8
e
r
o
f
e
b
t
i
a
w
l
l
i
w
r
e
m
i
t
g
o
d
h
c
t
a
w
e
h
t
e
h
t
t
e
s
e
r
d
n
a
e
d
o
m
m
r
a
l
a
o
t
s
e
o
g
t
i
t
l
u
a
f
e
D
.
g
n
i
t
t
e
s
e
f
a
s
e
h
t
o
t
y
c
n
e
u
q
e
r
f
6
.
4
=
s
m
0
9
2
X
6
1
s
i
p
u
r
e
w
o
p
t
a
.
s
d
n
o
c
e
s
6
t
i
B
0
5
t
i
B
0
4
t
i
B
1
3
t
i
B
0
2
t
i
B
0
1
t
i
B
0
0
t
i
B
0
6
ICS94208
0613A--01/13/03
Notes:
1. PWD = Power on Default
Byte 11: VCO Frequency Control Register
Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
0
t
i
B
r
e
d
i
v
i
D
O
C
V
6
t
i
B
X
6
t
i
B
r
e
d
i
v
i
D
F
E
R
5
t
i
B
X
5
t
i
B
r
e
d
i
v
i
D
F
E
R
4
t
i
B
X
4
t
i
B
r
e
d
i
v
i
D
F
E
R
3
t
i
B
X
3
t
i
B
r
e
d
i
v
i
D
F
E
R
2
t
i
B
X
2
t
i
B
r
e
d
i
v
i
D
F
E
R
1
t
i
B
X
1
t
i
B
r
e
d
i
v
i
D
F
E
R
0
t
i
B
X
0
t
i
B
r
e
d
i
v
i
D
F
E
R
Byte 12: VCO Frequency Control Register
Note: The decimal representation of these 9 bits (Byte
12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO
divider value. For example if VCO divider value of 36
is desired, user need to program 36 - 8 = 28, namely, 0,
00011100 into byte 12 bit & byte 11 bit 7.
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
8
t
i
B
r
e
d
i
v
i
D
O
C
V
6
t
i
B
X
7
t
i
B
r
e
d
i
v
i
D
O
C
V
5
t
i
B
X
6
t
i
B
r
e
d
i
v
i
D
O
C
V
4
t
i
B
X
5
t
i
B
r
e
d
i
v
i
D
O
C
V
3
t
i
B
X
4
t
i
B
r
e
d
i
v
i
D
O
C
V
2
t
i
B
X
3
t
i
B
r
e
d
i
v
i
D
O
C
V
1
t
i
B
X
2
t
i
B
r
e
d
i
v
i
D
O
C
V
0
t
i
B
X
1
t
i
B
r
e
d
i
v
i
D
O
C
V
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
7
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
6
t
i
B
X
6
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
5
t
i
B
X
5
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
4
t
i
B
X
4
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
3
t
i
B
X
3
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
2
t
i
B
X
2
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
1
t
i
B
X
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
0
t
i
B
X
0
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
d
e
v
r
e
s
e
R
6
t
i
B
X
d
e
v
r
e
s
e
R
5
t
i
B
X
d
e
v
r
e
s
e
R
4
t
i
B
X
2
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
3
t
i
B
X
1
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
2
t
i
B
X
0
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
1
t
i
B
X
9
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
0
t
i
B
X
8
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
1
l
o
r
t
n
o
C
w
e
k
S
2
1
M
A
R
D
S
6
t
i
B
0
5
t
i
B
0
l
o
r
t
n
o
C
w
e
k
S
)
0
:
1
1
(
M
A
R
D
S
4
t
i
B
1
3
t
i
B
1
l
o
r
t
n
o
C
w
e
k
S
1
T
K
L
C
U
P
C
2
t
i
B
1
1
t
i
B
1
l
o
r
t
n
o
C
w
e
k
S
)
0
(
T
&
C
K
L
C
U
P
C
0
t
i
B
0
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
d
e
v
r
e
s
e
R
6
t
i
B
X
d
e
v
r
e
s
e
R
5
t
i
B
X
d
e
v
r
e
s
e
R
4
t
i
B
X
d
e
v
r
e
s
e
R
3
t
i
B
X
d
e
v
r
e
s
e
R
2
t
i
B
X
d
e
v
r
e
s
e
R
1
t
i
B
X
d
e
v
r
e
s
e
R
0
t
i
B
X
d
e
v
r
e
s
e
R
7
ICS94208
0613A--01/13/03
Byte 17: Output Rise/Fall Time Select Register
Byte 18: Output Rise/Fall Time Select Register
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
)
0
:
3
(
I
C
P
6
t
i
B
0
5
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
F
_
I
C
P
4
t
i
B
0
3
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
1
T
K
L
C
U
P
C
2
t
i
B
0
1
t
i
B
0
)
d
e
v
r
e
s
e
R
(
0
t
i
B
0
l
o
r
t
n
o
C
e
t
a
r
w
e
l
S
0
T
K
L
C
U
P
C
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
2
1
M
A
R
D
S
6
t
i
B
0
5
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
1
K
L
C
P
G
A
4
t
i
B
0
3
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
0
K
L
C
P
G
A
2
t
i
B
0
1
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
4
K
L
C
I
C
P
0
t
i
B
0
Byte 19: Output Rise/Fall Time Select Register
Byte 20: Output Rise/Fall Time Select Register
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
z
H
M
8
4
6
t
i
B
0
5
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
z
H
M
8
4
_
4
2
4
t
i
B
0
3
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
1
F
E
R
2
t
i
B
0
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
0
F
E
R
1
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
)
0
:
1
1
(
M
A
R
D
S
0
t
i
B
0
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
d
e
v
r
e
s
e
R
6
t
i
B
0
d
e
v
r
e
s
e
R
5
t
i
B
0
d
e
v
r
e
s
e
R
4
t
i
B
0
d
e
v
r
e
s
e
R
3
t
i
B
0
d
e
v
r
e
s
e
R
2
t
i
B
0
d
e
v
r
e
s
e
R
1
t
i
B
0
d
e
v
r
e
s
e
R
0
t
i
B
0
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
0
T
K
L
C
U
P
C
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)
-0.5
To program the VCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy
programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by
writing to byte 0, or using initial hardware power up frequency.
2. Write 0001, 1001 (19
H
) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew
rate.
7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be
changed again, user only needs to write to byte 11 and 12 unless the system is to reboot.
8
ICS94208
0613A--01/13/03
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . 0C to +70C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115C
Storage Temperature . . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Volt age VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+ 0.3
V
Input Low Voltage
V
IL
V
SS
- 0.3
0.8
V
Input High Current
I
IH
V
IN
= VDD
5
A
Input Low Current
I
IL1
V
IN
=0 V; Inputs with no pull-up
resistors
-5
uA
Input Low Current
I
IL2
V
IN
=0 V; Inputs with pull-up resistors
-200
uA
I
DD3.3OP66
C
L
=0 pF; Select@ 66MHz
87
I
DD3.3OP100
C
L
=0 pF; Select@ 100MHz
91
180
mA
I
DD3.3OP133
C
L
=0 pF; Select@ 133MHz
104
Power Down
PD
3.25
5
mA
Input frequency
Fi
V
DD
= 3.3 V;
12
14.318
16
MHz
C
IN
Logic Inputs
5
pF
C
INX
X1 & X2 pins
27
45
pF
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target Freq.
3
ms
Skew
1
t
CPU-PCI
V
T
= 50% to 1.5V
1
2
4
ns
1
Guaranteed by design, not 100% tested in production.
Operating Supply Current
Input Capacitance
1
9
ICS94208
0613A--01/13/03
Electrical C haracteristics - CPU C LK (Open D rain Differential)
TA = 0 - 70C; VDD = 3.3 V +/-5% ; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
Z
0
V
O
= V
X
Output High Voltage
V
OH2B
Termination to Vpull-up(external)
1
1.2
V
Output Low Voltage
V
OL2B
Termination to Vpull-up(external)
0.4
V
Output Low Current
I
OL2B
V
OL
= 0.3 V
18
mA
Rise Time
1
t
r2A
V
OL
= 0.3 V, V
OH
= 1.2 V
0.53
0.9
ns
Fall Time
1
t
f2A
V
OH
= 1.2 V, V
OL
= 0.3 V
0.53
0.9
ns
Differential voltage-AC
1
V
DIF
Note 2
0.4
V p u
(ext ernal) +
0 .6
V
Differential voltage-DC
1
V
DIF
Note 2
0.2
V p u
(ext ernal) +
0 .6
V
Differential Crossover
V
X
Note 3
550
1100
mV
Duty Cycle
1
d
t2A
V
T
= 50%
45
51
55
%
Skew
1
t
s k 2A
V
T
= 50%
230
375
ps
Jitter, Cycle-to-cycle
1
t
jc y c -c y c 2A
V
T
= VX
200
250
ps
Jitter, Absolute
1
t
jabs 2A
V
T
= 50%
-250
250
ps
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltage (VTR-VCP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level
3 - Vpullup(external)=1.5V, Min=Vpullup(External)/2-150mV, Max=Vpullup(external)/2+150mV
Electrical Characteristics - CPUCLK(Single-ended Open Drain)
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH2B
Termination to Vpull-up(external)
1
1.2
V
Output Low Voltage
V
OL2B
Termination to Vpull-up(external)
0.4
V
Output Low Current
I
OL2B
V
OL
= 0.3 V
18
mA
Rise Time
1
t
r2A
V
OL
= 0.3 V, V
OH
= 1.2 V
0.53
0.9
ns
Fall Time
1
t
f2A
V
OH
= 1.2 V, V
OL
= 0.3 V
0.53
0.9
ns
Duty Cycle
1
d
t2A
V
T
= 50%
45
51
55
%
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2A
V
T
= VX
200
250
ps
Jitter, Absolute
1
t
jabs2A
V
T
= 50%
-250
250
ps
1 - Guaranteed by design, not 100% tested in production.
10
ICS94208
0613A--01/13/03
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
R
DSP2A
1
V
O
= V
DD
*0.5
10
20
Output Impedance
R
DSN2A
1
V
O
= V
DD
*0.5
10
20
Output High Voltage
V
OH2A
IOH = -28mA
2.4
V
Output Low Voltage
V
OL2A
IOL = 19mA
0.4
V
Output High Current
I
OH2A
V
OH
= 2.0 V
-42
mA
Output Low Current
I
OL2A
V
OL
= 0.8 V
33
mA
Rise Time
1
t
r2A
V
OL
= 0.4 V, V
OH
= 2.4 V
1.03
2
ns
Fall Time
1
t
f2A
V
OH
= 2.4 V, V
OL
= 0.4 V
0.87
2
ns
Duty Cycle
1
d
t2A
V
T
= 1.5V
45
49
55
%
Skew Window
(0:11)
t
sk2A
V
T
= 1.5V
217
250
ps
Skew Window
(0:12)
t
sk2A
V
T
= 1.5V
282
500
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2A
VT = 1.5V
217
250
ps
1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK_F, PCICLK(0:4)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
R
DSP2A
1
V
O
= V
DD
*0.5
12
55
Output Impedance
R
DSN2A
1
V
O
= V
DD
*0.5
12
55
Output High Voltage
V
OH1
I
OH
= -18 mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= 9.4 mA
0.4
V
Output High Current
I
OH1
V
OH
= 2.0 V
-16
mA
Output Low Current
I
OL1
V
OL
= 0.8 V
19
mA
Rise Time
1
t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V
2.41
2.5
ns
Fall Time
1
t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V
2.43
2.5
ns
Duty Cycle
1
d
t1
V
T
= 1.5V
45
51.7
55
%
Skew
1
(window)
T
sk1
1
V
T
= 1.5V
207
500
ps
Jitter, Cycle-to-cycle
1
t
jsl1
VT = 1.5V
400
500
ps
1
Guaranteed by design, not 100% tested in production.
11
ICS94208
0613A--01/13/03
Electrical Characteristics - AGPCLK
TA = 0 - 70C; VDD = 3.3 V +/-5% ; CL = 20 pF (unless otherwise stated)
PARAMETER
S YMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High V oltage
V
OH5
I
OH
= -11 mA
2.6
V
Output Low Voltage
V
OL5
I
OL
= 9.4 mA
0.4
V
Output High Current
I
OH5
V
OH
= 2.0 V
-16
mA
Output Low Current
I
OL5
V
OL
= 0.8 V
19
mA
Rise Time
1
t
r5
V
OL
= 0.4 V , V
OH
= 2.4 V
1.63
2
ns
Fall Time
1
t
f5
V
OH
= 2.4 V, V
OL
= 0.4 V
1.69
2
ns
Duty Cycle
1
d
t5
V
T
= 1.5V
45
52
55
%
Skew
1
(window)
T
s k
1
V
T
= 1.5V
60
175
ps
Jitter, Cycle-to-cycle
1
t
jc y c -c y c 2B
VT = 1.5V
349
500
ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz,48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
R
DSP5
1
V
O
= V
DD
*0.5
20
60
Output Impedance
R
DSN5
1
V
O
= V
DD
*0.5
20
60
Output High Voltage
V
OH5
I
OH
= -16 mA
2.4
V
Output Low Voltage
V
OL5
I
OL
= 9 mA
0.4
V
Output High Current
I
OH5
V
OH
= 2.0 V
-20
mA
Output Low Current
I
OL5
V
OL
= 0.8 V
10
mA
Rise Time
1
t
r5
1
V
OL
= 0.4 V, V
OH
= 2.4 V
1.43
4
ns
Fall Time
1
t
f5
1
V
OH
= 2.4 V, V
OL
= 0.4 V
1.56
4
ns
Duty Cycle
1
d
t5
1
V
T
= 1.5V
45
52
55
%
Jitter, Cycle to cycle
t
jls5
1
V
T
= 1.5V
256
500
ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF(0:1)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH5
I
OH
= -12 mA
2.4
V
Output Low Voltage
V
OL5
I
OL
= 9 mA
0.4
V
Output High Current
I
OH5
V
OH
= 2.0 V
-22
mA
Output Low Current
I
OL5
V
OL
= 0.8 V
16
mA
Rise Time
1
t
r5
V
OL
= 0.4 V, V
OH
= 2.4 V
1.97
4
ns
Fall Time
1
t
f5
V
OH
= 2.4 V, V
OL
= 0.4 V
2.07
4
ns
Duty Cycle
1
d
t5
V
T
= 1.5V
45
54.8
55
%
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
V
T
= 1.5V
2609
3000
ps
1
Guaranteed by design, not 100% tested in production.
12
ICS94208
0613A--01/13/03
General I
2
C serial interface information for the ICS94208
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending Byte 0 through Byte 28
(see Note 2)
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends Byte 0 through byte 6 (default)
ICS clock sends Byte 0 through byte X (if X
(H)
was
written to byte 6).
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
*See notes on the following page
.
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 18
ACK
Byte 19
ACK
Byte 20
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
If 7
H
has been written to B6
Byte 7
ACK
If 1A
H
has been written to B6
Byte18
ACK
If 1B
H
has been written to B6
Byte 19
ACK
If 1C
H
has been written to B6
Byte 20
ACK
Stop Bit
How to Read:
13
ICS94208
0613A--01/13/03
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4.
The input is operating at 3.3V logic levels.
5.
The data byte format is 8 bit bytes.
6.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
Notes:
Brief I
2
C registers description for ICS94208
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Functionality &
Frequency Select
Register
0
Output frequency, hardware / I
2
C
frequency select, spread spectrum &
output enable control register.
See individual
byte
description
Output Control Registers
1-6
Active / inactive output control
registers/latch inputs read back.
See individual
byte
description
Vendor ID & Revision ID
Registers
7
Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.
See individual
byte
description
Byte Count
Read Back Register
8
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00
H
to
this byte.
08
H
Watchdog Timer
Count Register
9
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
10
H
Watchdog Control
Registers
10 Bit [6:0]
Watchdog enable, watchdog status
and programmable 'safe' frequency'
can be configured in this register.
000,0000
VCO Control Selection
Bit
10 Bit [7]
This bit select whether the output
frequency is control by
hardware/byte 0 configurations or
byte 11&12 programming.
0
VCO Frequency Control
Registers
11-12
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
Depended on
hardware/byte
0 configuration
Spread Spectrum
Control Registers
13-14
These registers control the spread
percentage amount.
Depended on
hardware/byte
0 configuration
Group Skews Control
Registers
15-16
Increment or decrement the group
skew amount as compared to the
initial skew.
See individual
byte
description
Output Rise/Fall Time
Select Registers
17-20
These registers will control the
output rise and fall time.
See individual
byte
description
14
ICS94208
0613A--01/13/03
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS94208
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and
stored into a 5-bit internal data latch. At the end of Power-
On reset, (see AC characteristics for timing values), the
device changes the mode of operations for these pins to
an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
W
8.2K
W
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
15
ICS94208
0613A--01/13/03
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CPU_STOP# is synchronized by the ICS94208. The minimum that the CPU clock is enabled (CPU_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS94208.
3. All other clocks continue to run undisturbed.
PCICLK
CPUCLKT
CPUCLKC
PD# (High)
CPU_STOP#
INTERNAL
CPUCLK
16
ICS94208
0613A--01/13/03
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94208. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS94208 internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94208 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94208.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
17
ICS94208
0613A--01/13/03
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power
operation. SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS94208. All other clocks will
continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and
start in such a manner that guarantees the high pulse width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the SDRAM clocks inside the ICS94208.
3. All other clocks continue to run undisturbed.
18
ICS94208
0613A--01/13/03
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping
and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94208 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
19
ICS94208
0613A--01/13/03
MIN
MAX
MIN
MAX
A
2.40
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.00
10.70
.395
.420
E1
7.40
7.60
.291
.299
e
h
0.40
0.65
.015
.025
l
0.50
1.00
.020
.040
n
0
8
0
8
VARIATIONS
MIN
MAX
MIN
MAX
48
15.75
16.00
.620
.630
SYMBOL
SEE VARIATIONS
0.025 BASIC
SEE VARIATIONS
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
SEE VARIATIONS
0.65 BASIC
N
D mm.
D (inch)
SEE VARIATIONS
Ordering Information
ICS94208yF-T
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - T
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
h x 45
h x 45
E1
E
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
- C -
b
.10 (.004) C
.10 (.004) C
c
L
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