ICS94209
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
94209 RevA - 04/27/01
Programmable Frequency Generator & Integrated Buffers for Pentium III Processor
Block Diagram
Recommended Application:
Single chip clock solution 630S chipset.
Output Features:
3 - CPU @ 2.5V
13 - SDRAM @ 3.3V
6- PCI @3.3V,
2 - AGP @ 3.3V
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I
2
C
(Default is 24MHz)
2- REF @3.3V, 14.318MHz.
Features:
Programmable ouput frequency.
Programmable ouput rise/fall time.
Programmable SDRAM and CPU skew.
Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
FS pins for frequency select
Skew Specifications:
CPU - CPU: < 175ps
SDRAM - SDRAM < 250ps (except SDRAM12)
PCI - PCI: < 500ps
CPU (early) - PCI: 1-4ns (typ. 2ns)
Functionality
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1
These are double strength.
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK (2:0)
SDRAM (12:0)
PCICLK (4:0)
AGP (1:0)
PCICLK_F
2
5
13
3
2
X1
X2
XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
PCI
DIVDER
Stop
Stop
Stop
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
AGP_SEL
Control
Logic
Config.
Reg.
/ 2
REF(1:0)
AGP
DIVDER
VDDA
(AGPSEL)REF0
*(FS3)REF1
GND
X1
X2
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
VDDAGP
AGPCLK0
AGPCLK1
GND
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
1
1
*
VDDL
CPUCLK0
CPUCLK1
CPUCLK2
GND
VDDSDR
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GND
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR
ICS94209
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
0
0
0
0
66.67
66.67
33.33
66.67
50.00
0
0
0
1
100.00 100.00
33.33
66.67
50.00
0
0
1
0
166.67 166.67
33.33
66.66
55.56
0
0
1
1
133.33 133.33
33.33
66.67
50.00
0
1
0
0
66.67
100.00
33.33
66.67
50.00
0
1
0
1
100.00
66.67
33.33
66.67
50.00
0
1
1
0
100.00 133.33
33.33
66.67
50.00
0
1
1
1
133.33 100.00
33.33
66.67
50.00
1
0
0
0
112.00 112.00
33.60
67.20
56.00
1
0
0
1
124.00 124.00
31.00
62.00
46.50
1
0
1
0
138.00 138.00
34.50
69.00
51.75
1
0
1
1
150.00 150.00
30.00
60.00
50.00
1
1
0
0
66.67
133.33
33.33
66.67
50.00
1
1
0
1
100.00 150.00
30.00
60.00
50.00
1
1
1
0
150.00 100.00
30.00
60.00
50.00
1
1
1
1
160.00 120.00
30.00
60.00
48.00
AGP
SEL = 0
AGP
SEL = 1
CPU
SDRAM PCICLK
FS3 FS2 FS1 FS0
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS94209
Third party brands and names are the property of their respective owners.
General Description
Pin Configuration
The ICS94209 is a single chip clock solution for desktop
designs using 630S chipsets. It provides all necessary clock
signals for such a system.
The ICS94209 belongs to ICS new generation of
programmable system clock generators. It employs serial
programming I
2
C interface as a vehicle for changing output
functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread
spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety
'Watchdog Timer' technology which will reset the frequency
to a safe setting if the system becomes unstable from over
clocking.
Power Groups
Analog
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF
E
D
O
M
1
2
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9
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8
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1
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#
P
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_
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A
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D
S
#
D
P
MODE Pin Power Management Control Input
PIN N U MB ER
PIN N A ME
TY PE
D ES C R IPTION
1, 7, 15, 22, 25,
35, 43
V D D
P WR
3.3V P ow er supply for SD RA M output buffers, PCI output buffers,
reference output buffers and 48M H z output
A G P S EL
IN
A G P frequency select pin.
REF0
O U T
14.318 M H z reference clock.
F S3
IN
F requency select pin.
REF1
O U T
14.318 M H z reference clock.
4, 14, 18, 19, 29,
32, 39, 44
G N D
P WR
G round pin for 3V outputs.
5
X 1
IN
C rystal input,nominally 14.318M H z.
6
X 2
O U T
C rystal output, nominally 14.318M H z.
F S1
IN
F requency select pin.
PCIC LK _F
O U T
P CI clock output, not affected by P CI_STO P #
F S2
IN
F requency select pin.
PCIC LK 0
O U T
P CI clock output.
13, 12, 11, 10
PCICLK (4:1)
O U T
P CI clock outputs.
17, 16,
A G P (1:0)
O U T
A G P outputs defined as 2X PC I. These may not be stopped.
F S0
IN
F requency select pin.
48M H z
O U T
48M H z output clock
M O D E
IN
P in 27, 28, 30, & 31 function select pin
0=D esktop 1=M obile mode
24_48M H z
O U T
C lock output for super I/O /U S B default is 24M H z
23
SD A TA
I/O
D ata pin for I
2
C circuitry 5V tolerant
24
S CLK
IN
C lock pin of I
2
C circuitry 5V tolerant
CP U _S TO P #
IN
S tops all PCICLK s besides the PCICLK _F clocks at logic 0 level, w hen input
is low and M O D E pin is in M obile mode
SD RA M 11
O U T
S D RA M clock output
PCI_STO P #
IN
S tops all CPU CLK s clocks at logic 0 level, w hen input is low and M O D E pin
is in M obile mode
SD RA M 10
O U T
S D RA M clock output
S D R A M 9
O U T
S D RA M clock output
S D RA M _STO P #
IN
S tops all SD RA M clocks at logic 0 level, w hen input is low and M O D E pin
is in M obile mode
P D #
IN
A synchronous active low input pin used to pow er dow n the device into a low
pow er state. The internal clocks are disabled and the V CO and the crystal are
stopped. The latency of the pow er dow n w ill not be greater than 3ms.
S D R A M 8
O U T
S D RA M clock output
26 33, 34, 36, 37,
38, 40, 41, 42
SD RA M (12, 7:0)
O U T
S D RA M clock outputs
45, 46, 47
CP U C LK (2:0)
O U T
C PU clock outputs.
48
V D D L
P WR
P ow er pin for the CP U CLK s. 2.5V
31
20
2
8
9
21
3
30
27
28
3
ICS94209
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: PWD = Power-Up Default
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
I
2
C is a trademark of Philips Corporation
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0
1
0
0
.
5
0
1
0
0
.
0
4
1
0
0
.
5
3
0
0
.
0
7
0
5
.
2
5
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
1
1
0
0
0
.
5
0
1
0
5
.
7
5
1
0
5
.
1
3
0
0
.
3
6
0
5
.
2
5
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
1
1
1
3
3
.
5
3
1
0
5
.
1
0
1
3
8
.
3
3
7
6
.
7
6
5
7
.
0
5
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
3
t
i
B
s
t
u
p
n
I
d
e
h
c
t
a
L
,t
c
e
l
e
s
e
r
a
w
d
r
a
h
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
0
4
:
7
2
,
t
i
B
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
1
0
1
t
i
B
l
a
m
r
o
N
-
0
d
e
l
b
a
n
E
m
u
r
t
c
e
p
S
d
a
e
r
p
S
-
1
1
0
t
i
B
g
n
i
n
n
u
R
-
0
s
t
u
p
t
u
o
l
l
a
e
t
a
t
s
i
r
T
-
1
0
4
ICS94209
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
3
1
1
4
K
L
C
I
C
P
4
t
i
B
2
1
1
3
K
L
C
I
C
P
3
t
i
B
1
1
1
2
K
L
C
I
C
P
2
t
i
B
0
1
1
1
K
L
C
I
C
P
1
t
i
B
9
1
0
K
L
C
I
C
P
0
t
i
B
8
1
F
_
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
1
2
1
z
H
M
8
4
_
4
2
5
t
i
B
0
2
1
z
H
M
8
4
4
t
i
B
6
2
1
2
1
M
A
R
D
S
3
t
i
B
7
2
1
1
1
M
A
R
D
S
2
t
i
B
8
2
1
0
1
M
A
R
D
S
1
t
i
B
0
3
1
9
M
A
R
D
S
0
t
i
B
1
3
1
8
M
A
R
D
S
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
3
S
F
6
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
2
S
F
5
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
1
S
F
4
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
0
S
F
3
t
i
B
3
1
0
F
E
R
2
t
i
B
2
1
1
F
E
R
1
t
i
B
7
1
1
1
K
L
C
P
G
A
0
t
i
B
6
1
1
0
K
L
C
P
G
A
Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
3
3
1
7
M
A
R
D
S
6
t
i
B
4
3
1
6
M
A
R
D
S
5
t
i
B
6
3
1
5
M
A
R
D
S
4
t
i
B
7
3
1
4
M
A
R
D
S
3
t
i
B
8
3
1
3
M
A
R
D
S
2
t
i
B
0
4
1
2
M
A
R
D
S
1
t
i
B
1
4
1
1
M
A
R
D
S
0
t
i
B
2
4
1
0
M
A
R
D
S
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
8
4
_
4
2
l
e
S
)
z
H
M
8
4
:
0
,
z
H
M
4
2
:
1
(
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
7
4
1
0
K
L
C
U
P
C
2
t
i
B
6
4
1
1
K
L
C
U
P
C
1
t
i
B
5
4
1
2
K
L
C
U
P
C
0
t
i
B
-
1
d
e
v
r
e
s
e
R
5
ICS94209
Third party brands and names are the property of their respective owners.
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
d
e
v
r
e
s
e
R
6
t
i
B
-
0
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
0
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
0
d
e
v
r
e
s
e
R
1
t
i
B
-
0
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
3
,
2
0
X
2
=
1
,
X
1
=
0
h
t
g
n
e
r
t
s
F
E
R
6
t
i
B
5
4
0
l
o
r
t
n
o
C
-
p
o
t
S
-
2
K
L
C
U
P
C
,
2
K
L
C
U
P
C
l
o
r
t
n
o
c
l
l
i
w
#
P
O
T
S
_
U
P
C
=
0
w
o
l
s
i
#
P
O
T
S
_
U
P
C
f
i
n
e
v
e
g
n
i
n
n
u
r
e
e
r
f
s
i
2
K
L
C
U
P
C
=
1
5
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
L
E
S
P
G
A
4
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
E
D
O
M
3
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
#
P
O
T
S
_
U
P
C
2
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
#
P
O
T
S
_
I
C
P
1
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
#
P
O
T
S
_
M
A
R
D
S
0
t
i
B
-
0
e
l
g
g
o
T
d
e
e
p
S
P
G
A
,
g
n
i
t
t
e
s
t
u
p
n
i
h
c
t
a
l
y
b
d
e
n
i
m
r
e
t
e
d
e
b
l
l
i
w
)
2
n
i
p
(
L
E
S
P
G
A
=
0
g
n
i
t
t
e
s
t
u
p
n
i
h
c
t
a
l
f
o
e
t
i
s
o
p
p
o
e
b
l
l
i
w
L
E
S
P
G
A
=
1
Byte 8: Byte Count and Read Back Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
d
e
v
r
e
s
e
R
6
t
i
B
-
0
d
e
v
r
e
s
e
R
5
t
i
B
-
0
d
e
v
r
e
s
e
R
4
t
i
B
-
0
d
e
v
r
e
s
e
R
3
t
i
B
-
0
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
0
d
e
v
r
e
s
e
R
0
t
i
B
-
0
d
e
v
r
e
s
e
R
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000 entry in
byte0.
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
q
e
r
f
2
1
&
1
1
B
=
1
/
q
e
r
f
0
B
/
w
H
=
0
6
t
i
B
0
e
l
b
a
n
e
=
1
/
e
l
b
a
s
i
d
=
0
e
l
b
a
n
E
D
W
5
t
i
B
0
m
r
a
l
a
=
1
/
l
a
m
r
o
n
=
0
s
u
t
a
t
S
D
W
4
t
i
B
0
2
t
i
b
0
e
t
y
B
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
3
t
i
B
0
3
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
2
t
i
B
0
2
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
1
t
i
B
0
1
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
0
t
i
B
0
0
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
Byte 9: Watchdog Timer Count Register
ti
B
D
W
P
n
o
it
p
i
r
c
s
e
D
7
ti
B
0
e
s
e
h
t
f
o
n
o
it
a
t
n
e
s
e
r
p
e
r
l
a
m
i
c
e
d
e
h
T
s
m
1
r
o
s
m
0
9
2
o
t
d
n
o
p
s
e
r
r
o
c
s
ti
b
8
e
r
o
f
e
b
ti
a
w
ll
i
w
r
e
m
it
g
o
d
h
c
t
a
w
e
h
t
e
h
t
t
e
s
e
r
d
n
a
e
d
o
m
m
r
a
l
a
o
t
s
e
o
g
ti
tl
u
a
f
e
D
.
g
n
it
t
e
s
e
f
a
s
e
h
t
o
t
y
c
n
e
u
q
e
r
f
6
.
4
=
s
m
0
9
2
X
6
1
s
i
p
u
r
e
w
o
p
t
a
.
s
d
n
o
c
e
s
6
ti
B
0
5
ti
B
0
4
ti
B
1
3
ti
B
0
2
ti
B
0
1
ti
B
0
0
ti
B
0
6
ICS94209
Third party brands and names are the property of their respective owners.
Notes:
1. PWD = Power on Default
Byte 11: VCO Frequency Control Register
Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .
ti
B
D
W
P
n
o
it
p
i
r
c
s
e
D
7
ti
B
X
0
ti
B
r
e
d
i
v
i
D
O
C
V
6
ti
B
X
6
ti
B
r
e
d
i
v
i
D
F
E
R
5
ti
B
X
5
ti
B
r
e
d
i
v
i
D
F
E
R
4
ti
B
X
4
ti
B
r
e
d
i
v
i
D
F
E
R
3
ti
B
X
3
ti
B
r
e
d
i
v
i
D
F
E
R
2
ti
B
X
2
ti
B
r
e
d
i
v
i
D
F
E
R
1
ti
B
X
1
ti
B
r
e
d
i
v
i
D
F
E
R
0
ti
B
X
0
ti
B
r
e
d
i
v
i
D
F
E
R
Byte 12: VCO Frequency Control Register
Note: The decimal representation of these 9 bits (Byte 12
bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO divider
value. For example if VCO divider value of 36 is desired,
user need to program 36 - 8 = 28, namely, 0, 00011100 into
byte 12 bit & byte 11 bit 7.
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
8
t
i
B
r
e
d
i
v
i
D
O
C
V
6
t
i
B
X
7
t
i
B
r
e
d
i
v
i
D
O
C
V
5
t
i
B
X
6
t
i
B
r
e
d
i
v
i
D
O
C
V
4
t
i
B
X
5
t
i
B
r
e
d
i
v
i
D
O
C
V
3
t
i
B
X
4
t
i
B
r
e
d
i
v
i
D
O
C
V
2
t
i
B
X
3
t
i
B
r
e
d
i
v
i
D
O
C
V
1
t
i
B
X
2
t
i
B
r
e
d
i
v
i
D
O
C
V
0
t
i
B
X
1
t
i
B
r
e
d
i
v
i
D
O
C
V
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
ti
B
D
W
P
n
o
it
p
i
r
c
s
e
D
7
ti
B
X
7
ti
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
6
ti
B
X
6
ti
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
5
ti
B
X
5
ti
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
4
ti
B
X
4
ti
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
3
ti
B
X
3
ti
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
2
ti
B
X
2
ti
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
1
ti
B
X
1
ti
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
0
ti
B
X
0
ti
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
d
e
v
r
e
s
e
R
6
t
i
B
X
d
e
v
r
e
s
e
R
5
t
i
B
X
d
e
v
r
e
s
e
R
4
t
i
B
X
2
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
3
t
i
B
X
1
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
2
t
i
B
X
0
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
1
t
i
B
X
9
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
0
t
i
B
X
8
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
1
l
o
r
t
n
o
C
w
e
k
S
2
1
M
A
R
D
S
6
t
i
B
0
5
t
i
B
0
l
o
r
t
n
o
C
w
e
k
S
)
0
:
1
1
(
M
A
R
D
S
4
t
i
B
1
3
t
i
B
1
l
o
r
t
n
o
C
w
e
k
S
2
K
L
C
U
P
C
2
t
i
B
1
1
t
i
B
1
l
o
r
t
n
o
C
w
e
k
S
)
0
:
1
(
K
L
C
U
P
C
0
t
i
B
0
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
d
e
v
r
e
s
e
R
6
t
i
B
X
d
e
v
r
e
s
e
R
5
t
i
B
X
d
e
v
r
e
s
e
R
4
t
i
B
X
d
e
v
r
e
s
e
R
3
t
i
B
X
d
e
v
r
e
s
e
R
2
t
i
B
X
d
e
v
r
e
s
e
R
1
t
i
B
X
d
e
v
r
e
s
e
R
0
t
i
B
X
d
e
v
r
e
s
e
R
7
ICS94209
Third party brands and names are the property of their respective owners.
Byte 17: Output Rise/Fall Time Select Register
Byte 18: Output Rise/Fall Time Select Register
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
)
0
:
3
(
I
C
P
6
t
i
B
0
5
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
F
_
I
C
P
4
t
i
B
0
3
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
2
K
L
C
U
P
C
2
t
i
B
0
1
t
i
B
0
l
o
r
t
n
o
C
e
t
a
r
w
e
l
S
1
K
L
C
U
P
C
0
t
i
B
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
2
1
M
A
R
D
S
6
t
i
B
0
5
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
1
K
L
C
P
G
A
4
t
i
B
0
3
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
0
K
L
C
P
G
A
2
t
i
B
0
1
t
i
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
4
K
L
C
I
C
P
0
t
i
B
0
Byte 19: Output Rise/Fall Time Select Register
Byte 20: Output Rise/Fall Time Select Register
ti
B
D
W
P
n
o
it
p
i
r
c
s
e
D
7
ti
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
z
H
M
8
4
6
ti
B
0
5
ti
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
z
H
M
8
4
_
4
2
4
ti
B
0
3
ti
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
1
F
E
R
2
ti
B
0
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
0
F
E
R
1
ti
B
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
)
0
:
1
1
(
M
A
R
D
S
0
ti
B
0
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
d
e
v
r
e
s
e
R
6
t
i
B
0
d
e
v
r
e
s
e
R
5
t
i
B
0
d
e
v
r
e
s
e
R
4
t
i
B
0
d
e
v
r
e
s
e
R
3
t
i
B
0
d
e
v
r
e
s
e
R
2
t
i
B
0
d
e
v
r
e
s
e
R
1
t
i
B
0
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
0
K
L
C
U
P
C
0
t
i
B
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)
-0.5
To program the VCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by writing to
byte 0, or using initial hardware power up frequency.
2. Write 0001, 1001 (19
H
) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew rate.
7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be changed
again, user only needs to write to byte 11 and 12 unless the system is to reboot.
8
ICS94209
Third party brands and names are the property of their respective owners.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Volt age VDD = 3.3 V +/-5%VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+0.3
V
Input Low Voltage
V
IL
V
SS
-0.3
0.8
V
Supply Current
I
DD
C
L
=30 pF, CPU @ 66, 100 MHz
390
400
mA
Power Down
PD
300
600
A
Input frequency
Fi
V
DD
= 3.3 V;
12
14.318
16
MHz
Input Capacitance1
C
IN
Logic Inputs
5
pF
C
INX
X1 & X2 pins
27
45
pF
Transition Time
T
trans
To 1st crossing of target Freq.
3
Settling Time
T
S
From 1st crossing to 1% target Freq.
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target Freq.
3
ms
Skew
T
CPU-PCI
CPUV
T
= 1.5 V PCI V
T
=1.25V
1
1.9
4
ns
Skew
T
CPU-SDRAM
CPUV
T
= 1.5 V SDRAM V
T
=1.25
-500
-300
0
ps
1
Guaranteed by design, not 100% tested in production.
9
ICS94209
Third party brands and names are the property of their respective owners.
Electrical Characteristics - CPU
T
A
= 0 - 70C; V
DDL
= 2.5 V +/-5%; VDDL = 2.5 V +/-5%; C
L
= 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
1
R
DSP2B
V
O
= V
DD
*(0.5)
10
20
Output Impedance
1
R
DSN2B
V
O
= V
DD
*(0.5)
10
20
Output High Voltage
V
OH2B
I
OH
= -12.0 mA
2
V
Output Low Voltage
V
OL2B
I
OL
= 12 mA
0.4
V
Output High Current
I
OH2B
V
OH
= 1.7 V
-19
mA
Output Low Current
I
OL2B
V
OL
= 0.7 V
19
mA
Rise Time
1
t
r2B
V
OL
= 0.4 V, V
OH
= 2.0 V
0.4
1.2
1.6
ns
Fall Time
1
t
f2B
V
OH
= 2.0 V, V
OL
= 0.4 V
0.4
1.1
1.6
ns
Duty Cycle
1
d
t2B
V
T
= 1.25 V
45
46.9
55
%
Skew window
0:1
t
sk2B
V
T
= 1.25 V
43
175
ps
Skew window
0:2
t
sk2B
V
T
= 1.25 V
142
375
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc
V
T
= 1.25 V, CPU=66 MHz
177
250
ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24-48MHz
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%;VDDL = 2.5 V +/-5%; C
L
= 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
R
DSP5B
1
V
O
= V
DD
*(0.5)
20
60
Output Impedance
R
DSN5B
1
V
O
= V
DD
*(0.5)
20
60
Output High Voltage
V
OH15
I
OH
= -14 mA
2.4
V
Output Low Voltage
V
OL5
I
OL
= 6.0 mA
0.4
V
Output High Current
I
OH5
V
OH
= 2.0 V
-20
mA
Output Low Current
I
OL5
V
OL
= 0.8 V
10
mA
Rise Time
1
t
r5
V
OL
= 0.4 V, V
OH
= 2.4 V
0.4
1.45
4
ns
Fall Time
1
t
f5
V
OH
= 2.4 V, V
OL
= 0.4 V
0.4
1.5
4
ns
Duty Cycle
1
d
t5
V
T
= 1.5 V
45
52.5
55
%
Jitter
t
cycle to cycle
V
T
= 1.5 V
210
500
ps
1
Guaranteed by design, not 100% tested in production.
10
ICS94209
Third party brands and names are the property of their respective owners.
Electrical Characteristics - PCI
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; VDDL = 2.5 V +/-5%; C
L
= 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
R
DSP1B
1
V
O
= V
DD
*(0.5)
12
55
Output Impedance
R
DSN1B
1
V
O
= V
DD
*(0.5)
12
55
Output High Voltage
V
OH1
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= 1 mA
0.55
V
Output High Current
I
OH1
V
OH @ MIN
= 1.0 V
-29
mA
Output Low Current
I
OL1
V
OL @ MIN
= 1.95 V
29
mA
Rise Time
1
t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V
0.5
2.3
2.5
ns
Fall Time
1
t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V
0.5
2.3
2.5
ns
Duty Cycle
1
d
t1
V
T
= 1.5 V
45
51.2
55
%
Skew window
1
t
sk1
V
T
= 1.5 V
108
500
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc1
V
T
= 1.5 V
353
500
ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%;VDDL = 2.5 V +/-5%; C
L
= 20-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
R
DSP3B
1
V
O
= V
DD
*(0.5)
10
24
Output Impedance
R
DSN3B
1
V
O
= V
DD
*(0.5)
10
24
Output High Voltage
V
OH3
I
OH
= -18 mA
2.4
V
Output Low Voltage
V
OL3
I
OL
= 9.4 mA
0.4
V
Output High Current
I
OH3
V
OH
= 2.0 V
-46
mA
Output Low Current
I
OL3
V
OL
= 0.8V
mA
Rise Time
1
t
r3
V
OL
= 0.4 V, V
OH
= 2.4 V
0.8
1.6
ns
Fall Time
1
t
f3
V
OH
= 2.4 V, V
OL
= 0.4 V
0.8
1.6
ns
Duty Cycle
1
d
t3
V
T
= 1.5 V
45
48.5
55
%
Skew window
1(0:11)
t
sk3
V
T
= 1.5 V
192
250
ps
Skew window
1( 0:12)
t
sk3
V
T
= 1.5 V
290
500
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc3
V
T
= 1.5 V, CPU=66,100,133 MHz
173
250
ps
1
Guaranteed by design, not 100% tested in production.
11
ICS94209
Third party brands and names are the property of their respective owners.
Electrical Characteristics - AGP
T
A
= 0 - 70C; V
DD
=3.3V +/-5%; C
L
= 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
R
DSP4B
1
V
O
=V
DD
*(0.5)
12
55
Output Impedance
R
DSN4B
1
V
O
=V
DD
*(0.5)
12
55
Output High Voltage
V
OH4B
I
OH
= -18 mA
2
V
Output Low Voltage
V
OL4B
I
OL
= 18 mA
0.4
V
Output High Current
I
OH4B
V
OH
= 2.0 V
-19
mA
Output Low Current
I
OL4B
V
OL
= 0.8 V
19
mA
Rise Time
1
t
r4B
V
OL
= 0.4 V, V
OH
= 2.4 V
0.5
1.5
2
ns
Fall Time
1
t
f4B
V
OH
= 2.4 V, V
OL
= 0.4 V
0.5
1.6
2
ns
Duty Cycle
1
d
t4B
V
T
= 1.5 V
45
52.3
55
%
Skew window1
tsk
1
V
T
= 1.5 V
55.5
175
ps
Jitter Cyc-Cyc
tjcyc-cyc
1
V
T
= 1.5 V
239
500
ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70 C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH5
I
OH
= -12 mA
2.4
V
Output Low Voltage
V
OL5
I
OL
= 9 mA
0.4
V
Output High Current
I
OH5
V
OH
= 2.0 V
-22
mA
Output Low Current
I
OL5
V
OL
= 0.8 V
16
mA
Rise Time
1
t
r5
V
OL
= 0.4 V, VOH = 2.4 V
1.8
4
ns
Fall Time
1
t
f5
V
OH
= 2.4 V, VOL = 0.4 V
1.9
4
ns
Duty Cycle
1
d
t5
V
T
= 50%
45
54.5
55
%
1
Guaranteed by design, not 100% tested in production.
12
ICS94209
Third party brands and names are the property of their respective owners.
General I
2
C serial interface information for the ICS94209
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending Byte 0 through Byte 28
(see Note 2)
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends Byte 0 through byte 6 (default)
ICS clock sends Byte 0 through byte X (if X
(H)
was
written to byte 6).
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
*See notes on the following page
.
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 18
ACK
Byte 19
ACK
Byte 20
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
If 7
H
has been written to B6
Byte 7
ACK
If 1A
H
has been written to B6
Byte18
ACK
If 1B
H
has been written to B6
Byte 19
ACK
If 1C
H
has been written to B6
Byte 20
ACK
Stop Bit
How to Read:
13
ICS94209
Third party brands and names are the property of their respective owners.
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is
defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiver.
3.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4.
The input is operating at 3.3V logic levels.
5.
The data byte format is 8 bit bytes.
6.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
Notes:
Brief I
2
C registers description for ICS94209
Programmable System Frequency Generator
Register N ame
Byte
Description
PWD Default
Functionality & Frequency
Select Register
0
Output frequency, hardware / I
2
C
frequency select, spread spectrum &
output enable control register.
See individual
byte description
Output Control Registers
1-6
Active / inactive output control
registers/latch inputs read back.
See individual
byte description
Vendor ID & Revision ID
Registers
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
See individual
byte description
Byte Count
Read Back Register
8
Writing to this register will configure
byte count and how many byte w ill be
read back. Do not write 00
H
to this byte.
08
H
Watchdog Timer
Count Register
9
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
10
H
Watchdog Control Registers 10 Bit [6:0]
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
000,0000
VCO Control Selection Bit
10 Bit [7]
This bit select w hether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
0
VCO Frequency Control
Registers
11-12
These registers control the dividers ratio
into the phase detector and thus control
the V CO output frequency.
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
13-14
These registers control the spread
percentage amount.
Depended on
hardware/byte 0
configuration
Group Skews Control
Registers
15-16
Increment or decrement the group skew
amount as compared to the initial skew .
See individual
byte description
Output Rise/Fall Time
Select Registers
17-20
These registers will control the output
rise and fall time.
See individual
byte description
14
ICS94209
Third party brands and names are the property of their respective owners.
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS94209
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
W
8.2K
W
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
15
ICS94209
Third party brands and names are the property of their respective owners.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS94209. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS94209.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
16
ICS94209
Third party brands and names are the property of their respective owners.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94209. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS94209 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high
pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed.
PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94209 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94209.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
17
ICS94209
Third party brands and names are the property of their respective owners.
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power operation.
SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS94209. All other clocks will continue to run while
the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that
guarantees the high pulse width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to
the SDRAM clocks inside the ICS94209.
3. All other clocks continue to run undisturbed.
18
ICS94209
Third party brands and names are the property of their respective owners.
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94209 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
19
ICS94209
Third party brands and names are the property of their respective owners.
Ordering Information
ICS94209yF-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP - T
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
h x 45
h x 45
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
- C -
b
.10 (.004) C
.10 (.004) C
c
L
300 mil SSOP Package
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.03
10.68
.395
.420
E1
7.40
7.60
.291
.299
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
0
8
0
8
MIN
MAX
MIN
MAX
48
15.75
16.00
.620
.630
10-0034
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
SEE VARIATIONS
SEE VARIATIONS
0.635 BASIC
0.025 BASIC
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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