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Электронный компонент: ICS94215YF-T

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Integrated
Circuit
Systems, Inc.
ICS94215
0442C--07/03/02
Block Diagram
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
VIA KX/KT133 style chipset
Output Features:
1 - Differential pair open drain CPU clocks
1 - CPU clock @ 3.3V
13 - SDRAM @ 3.3V
6 - PCI @3.3V,
1 - 48MHz, @3.3V fixed.
1 - 24/48MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
Features:
Programmable ouput frequency.
Programmable ouput rise/fall time.
Programmable PCI_F and PCICLK skew.
Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
FS pins for frequency select
Programmable System Clock Chip for AMD - K7TM Processor
* Internal Pull-up Resistor of 120K to VDD
VDD1
REF0/CPU_STOP#*
GND
X1
X2
VDD2
*MODE/PCICLK_F
*FS3/PCICLK0
GND
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDD2
BUFFER IN
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLK
REF1/FS2*
GND
CPUCLK
GND
CPUCLKC0
CPUCLKT0
VDDCPU
PD#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
VDD4
48MHz/FS0*
24/48MHz/FS1*
ICS94215
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
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SEL24_48#
BUFFER IN
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
SDRAM (11:0)
PCICLK (4:0)
PCICLK_F
SDRAM_OUT
CPUCLKT0
CPUCLK
CPUCLKC0
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
SDATA
SCLK
FS (3:0)
PD#
CPU_STOP#
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
SDRAM
DRIVER
2
ICS94215
0442C--07/03/02
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
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3
ICS94215
0442C--07/03/02
General Description
The ICS94215 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all
clocks required for such a system.
The ICS94215 belongs to ICS new generation of programmable system clock generators. It employs serial
programming I
2
C interface as a vehicle for changing output functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system become unstable from over clocking.
Mode Pin - Power Management Input Control
7
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4
ICS94215
0442C--07/03/02
General I
2
C serial interface information for the ICS94215
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
 Controller (host) sends a dummy command code
ICS clock will acknowledge
 Controller (host) sends a dummy byte count
ICS clock will acknowledge
 Controller (host) starts sending Byte 0 through Byte 20
(see Note)
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
 ICS clock will send the byte count
 Controller (host) acknowledges
ICS clock sends Byte 0 through byte 8 (default)
 ICS clock sends Byte 0 through byte X (if X
(H)
was
written to byte 8).
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
*See notes on the following page
.
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 18
ACK
Byte 19
ACK
Byte 20
ACK
Stop Bit
How to Write:
Controlle r (Host)
ICS (Sla ve /Re ce ive r)
Start Bit
Address D3
(H )
A CK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
If 7
H
has been written to B8
Byte 7
ACK
If 12
H
has been written to B8
Byte18
ACK
If 13
H
has been written to B8
Byte 19
ACK
If 14
H
has been written to B8
Byte 20
ACK
Stop Bit
How to Read:
5
ICS94215
0442C--07/03/02
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4.
The input is operating at 3.3V logic levels.
5.
The data byte format is 8 bit bytes.
6.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
Notes:
Brief I
2
C registers description for ICS94215
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Functionality &
Frequency Select
Register
0
Output frequency, hardware / I
2
C
frequency select, spread spectrum &
output enable control register.
See individual
byte
description
Output Control
Registers
1-6
Active / inactive output control
registers/latch inputs read back.
See individual
byte
description
Vendor ID & Revision
ID Registers
7
Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.
See individual
byte
description
Byte Count
Read Back Register
8
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00
H
to
this byte.
08
H
Watchdog Timer
Count Register
9
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
10
H
Watchdog Control
Registers
10 Bit [6:0]
Watchdog enable, watchdog status
and programmable 'safe' frequency'
can be configured in this register.
000,0000
VCO Control Selection
Bit
10 Bit [7]
This bit select whether the output
frequency is control by
hardware/byte 0 configurations or
byte 11&12 programming.
0
VCO Frequency
Control Registers
11-12
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
Depended on
hardware/byte
0 configuration
Spread Spectrum
Control Registers
13-14
These registers control the spread
percentage amount.
Depended on
hardware/byte
0 configuration
Group Skews Control
Registers
15-16
Increment or decrement the group
skew amount as compared to the
initial skew.
See individual
byte
description
Output Rise/Fall Time
Select Registers
17-20
These registers will control the
output rise and fall time.
See individual
byte
description