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Integrated
Circuit
Systems, Inc.
ICS94235
Third party brands and names are the property of their respective owners.
Block Diagram
94235 Rev A 01/17/02
Functionality
Pin Configuration
Recommended Application:
Output Features:
1 - Differential pair open drain CPU clocks
1 - Single-ended open drain CPU clock
13 - SDRAM @ 3.3V
7 - PCI @ 3.3V
2 - AGP @ 3.3V
1 - 48MHz, @3.3V
1 - REF @ 3.3V, (selectable strength) through I
2
C
Features:
Programmable ouput frequency
Programmable ouput rise/fall time
Programmable CPU, SDRAM, PCI and AGP skew
Real time system reset output
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread percentage
Watchdog timer technology to reset system
if over-clocking causes malfunction
Uses external 14.318MHz crystal
Skew Specifications:
CPUT - CPUC: <250ps
PCI - PCI: <500ps
CPU - SDRAM: <350ps
SDRAM - SDRAM: <250ps
AGP - AGP: <250ps
AGP - PCI: <750ps
CPU - PCI: <3ns
48-Pin 300mil SSOP &
240mil TSSOP package
RESET#
*PD#
GND
X1
X2
AVDD
**FS0/REF0
VDD
**FS1/AGP0
AGP1
GND
*FS2/PCICLK_F
PCICLK0
PCICLK1
PCICLK2
GND
VDD
*MODE/PCICLK3
PCICLK4
PCICLK5
AVDD48
**FS3/48MHz
GND
SCLK
GND
CPUCLKT0
CPUCLKC0
CPUCLKT1
SDATA
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDD
GND
SDRAM6
SDRAM7
SDRAM8
SDRAM9
GND
VDD
SDRAM10(PCI_STOP#)*
SDRAM11
SDRAM12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PLL2
PLL1
Spread
Spectrum
48MHz
CPUCLKT (1:0)
SDRAM (12:0)
PCICLK (5:0)
AGP (1:0)
RESET#
2
6
13
2
PCICLK_F
CPUCLKC0
X1
X2
XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
PCI
DIVDER
AGP
DIVDER
Stop
Stop
Stop
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
MODE
Control
Logic
Config.
Reg.
REF0
Power Groups
FS3
FS2
FS1
FS0
CPU
SDRAM
PCI
AGP
0
0
0
0
66.66
66.66
33.33
66.66
0
0
0
1
66.66
100.00
33.33
66.66
0
0
1
0
100.00
66.66
33.33
66.66
0
0
1
1
100.00 100.00
33.33
66.66
0
1
0
0
100.00 133.33
33.33
66.66
0
1
0
1
120.00 120.00
30.00
60.00
0
1
1
0
133.33 100.00
33.33
66.66
0
1
1
1
133.33 133.33
33.33
66.66
1
0
0
0
90.00
90.00
30.00
60.00
1
0
0
1
100.90 100.90
33.63
67.27
1
0
1
0
100.00
66.66
33.33
66.66
1
0
1
1
100.00 100.00
33.33
66.66
1
1
0
0
100.00 133.33
33.33
66.66
0
1
0
1
126.00 126.00
31.50
63.00
1
1
1
0
133.33 100.00
33.33
66.66
1
1
1
1
133.33 133.33
33.33
66.66
ICS94235
Third party brands and names are the property of their respective owners.
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
RESET#
OUT
Real time system reset signal for frequency value or watchdog timmer
timeout. This signal is active low.
2
PD#
1
IN
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
4
X1
IN
Crystal input,nominally 14.318M Hz.
5
X2
OUT
Crystal output, nominally 14.318M Hz.
3, 11, 16, 23, 29,
34, 41, 48
GND
PWR
Ground pins
8, 17, 28, 35, 40
VDD
PWR
Power supply pins, nominal 3.3V
6
AVDD
PWR
Analog power supply pin, nominal 3.3V
FS0
2, 3
IN
Frequency select pin.
REF0
OUT
14.318 M Hz reference clock.
FS1
2, 3
IN
Frequency select pin.
AGP0
OUT
AGP outputs defined as 2X PCI. These may not be stopped.
10
AGP1
OUT
AGP outputs defined as 2X PCI. These may not be stopped.
PCICLK_F
OUT
Free running PCICLK not stoped by PCI_STOP#
FS2
1, 3
IN
Frequency select pin.
20, 19, 15, 14, 13
PCICLK
(5:4) (2:0)
OUT
PCI clock outputs.
PCICLK3
OUT
PCI clock output.
M ODE
1, 3
IN
Function select pin, 1=Desktop M ode, 0=M obile M ode.
21
AVDD48
PWR
Analog power supply pin, nominal 3.3V
FS3
2, 3
IN
Frequency select pin.
48M Hz
OUT
48M Hz output clock
24
SCLK
IN
Clock input of I
2
C input, 5V tolerant input
PCI_STOP#
1
IN
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low
SDRAM 10
OUT
SDRAM clock output.
25, 26, 30, 31, 32,
33, 36, 37, 38, 39,
42, 43
SDRAM
(12:11, 9:0 )
OUT
SDRAM clock outputs.
44
SDATA
I/O
Data pin for I
2
C circuitry 5V tolerant
45, 47
CPUCLKT (1:0)
OUT
"True" clocks of differential pair CPU outputs. These open drain outputs
need an external 1.5V pull-up.
46
CPUCLKC0
OUT
"Complementory" clocks of differential pair CPU outputs. This open drain
output need an external 1.5V pull-up.
9
7
27
12
22
18
ICS94235
Third party brands and names are the property of their respective owners.
General Description
Mode Pin - Power Management Input Control
8
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ICS94235
Third party brands and names are the property of their respective owners.
General I
2
C serial interface information for the ICS94235
How to Write:
How to Read:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 18
ACK
Byte 19
ACK
Byte 20
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave /Receive r)
Start Bit
Address D3
(H )
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
If 7
H
has been written to B8
Byte 7
ACK
If 12
H
has been written to B8
Byte18
ACK
If 13
H
has been written to B8
Byte 19
ACK
If 14
H
has been written to B8
Byte 20
ACK
Stop Bit
How to Read:
ICS94235
Third party brands and names are the property of their respective owners.
Brief I
2
C registers description for ICS94235
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Functionality & Frequency
Select Register
0
Output frequency, hardware / I
2
C
frequency select, spread spectrum &
output enable control register.
See individual
byte description
Output Control Registers
1-6
Active / inactive output control
registers/latch inputs read back.
See individual
byte description
Vendor ID & Revision ID
Registers
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
See individual
byte description
Byte Count
Read Back Register
8
Writing to this register will configure
byte count and how many byte will be
read back. Do not write 00
H
to this byte.
08
H
Watchdog Timer
Count Register
9
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
10
H
Watchdog Control Registers 10 Bit [6:0]
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
000,0000
VCO Control Selection Bit
10 Bit [7]
This bit select whether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
0
VCO Frequency Control
Registers
11-12
These registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
13-14
These registers control the spread
percentage amount.
Depended on
hardware/byte 0
configuration
Group Skews Control
Registers
15-16
Increment or decrement the group skew
amount as compared to the initial skew.
See individual
byte description
Output Rise/Fall Time
Select Registers
17-20
These registers will control the output
rise and fall time.
See individual
byte description
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