Integrated
Circuit
Systems, Inc.
ICS950104
Third party brands and names are the property of their respective owners.
Block Diagram
950104 Rev - 09/11/01
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
SIS630ST style chipset
Output Features:
1 - CPU clocks @ 2.5V
1 - Pair of differential CPU clocks @ 3.3V
9 - SDRAM @ 3.3V
7 - PCI @3.3V
1 - 48MHz, @3.3V
1 - 24/48MHz @ 3.3V
3 - REF @3.3V, (selectable strength) through I
2
C
Features:
Programmable ouput frequency
Programmable ouput rise/fall time
Programmable CPU, SDRAM, and PCI skew
Real time system reset output
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread percentage
Watchdog timer technology to reset system
if over-clocking causes malfunction
Uses external 14.318MHz crystal
Skew Specifications:
CPU - CPU: <250ps
PCI - PCI: <500ps
SDRAM - SDRAM: <250ps
CPU - SDRAM:<350ps
CPU - PCI: <3ns
Programmable
System Clock Chip for P
III
TM Processor
Notes:
REF0 can be 1X or 2X strength controlled by I
2
C.
* Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down of 120K to GND
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
PCICLK (5:0)
PCICLK_F
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CPU_STOP#
MODE
MULTSEL
Control
Logic
Config.
Reg.
/ 2
REF(2:0)
CPUCLK
SDRAM (9:0)
SDRAM
DIVDER
Stop
10
6
3
CPUCLKT0
CPUCLKC0
Stop
Advance Information
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
CPUCLKC0
CPUCLKT0
VDDCPU
GND
AVDD
X1
X2
**FS0/REF0
VDDREF
**FS1/REF1
REF2
GND
*FS2/PCICLK_F
PCICLK0
PCICLK1
PCICLK2
GND
VDDPCI
PCICLK3
PCICLK4
PCICLK5
AVDD48
**MULTSEL/24_48MHz
**FS3/48MHz
GND
IREF
GND
CPUCLK
VDDL
SDATA
SDRAM_STOP#
SDRAM0
SDRAM1
SDRAM2
SDRAM3
VDD
GND
SDRAM4
SDRAM5
SDRAM6
SDRAM7
GND
VDD
PCI_STOP#
CPU_STOP#
PD#/Vtt_PWRGD
SCLK
GND
*
*
*
#*
ICS950104
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
3
S
F
2
S
F
1
S
F
0
S
F
U
P
C
)
z
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(
M
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)
z
H
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z
H
M
(
0
0
0
0
6
.
6
6
0
.
0
0
1
3
.
3
3
0
0
0
1
0
.
0
0
1
0
.
0
0
1
3
.
3
3
0
0
1
0
0
.
0
5
1
0
.
0
0
1
5
.
7
3
0
0
1
1
3
.
3
3
1
0
.
0
0
1
3
.
3
3
0
1
0
0
8
.
6
6
6
.
3
3
1
4
.
3
3
0
1
0
1
0
.
0
0
1
3
.
3
3
1
3
.
3
3
0
1
1
0
0
.
0
0
1
0
.
0
5
1
5
.
7
3
0
1
1
1
3
.
3
3
1
3
.
3
3
1
3
.
3
3
1
0
0
0
8
.
6
6
8
.
6
6
4
.
3
3
1
0
0
1
0
.
7
9
0
.
7
9
3
.
2
3
1
0
1
0
0
.
0
7
0
.
5
0
1
0
.
5
3
1
0
1
1
0
.
5
9
0
.
5
9
7
.
1
3
1
1
0
0
0
.
5
9
7
.
6
2
1
7
.
1
3
1
1
0
1
0
.
2
1
1
0
.
2
1
1
3
.
7
3
1
1
1
0
0
.
7
9
3
.
9
2
1
2
.
2
3
1
1
1
1
2
.
6
9
2
.
6
9
1
.
2
3
2
ICS950104
Advance Information
Third party brands and names are the property of their respective owners.
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
3:
Internal Pull-down resistor of 120K to GND on indicated inputs.
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
CPUCLKC0
OUT
"Complementary" clocks of differential pair CPU outputs. These clocks are 180
out of phase with SDRAM clocks. These open drain outputs need an external
1.5V pull-up.
2
CPUCLKT0
OUT
"True" clocks of differential pair CPU outputs. These clocks are in phase with
SDRAM clocks. These open drain outputs need an external 1.5V pull-up.
3, 9, 18, 30, 37
VDD
PWR
Power supply pins, nominal 3.3V
4, 12, 17, 25, 31,
36, 46, 48
GND
PWR
Ground pins
5, 22
AVDD
PWR
Analog power supply for 3.3V
6
X1
IN
Crystal input,nominally 14.318MHz.
7
X2
OUT
Crystal output, nominally 14.318MHz.
FS0
2, 3
IN
Frequency select pin.
REF0
OUT
14.318 MHz reference clock.
FS1
2, 3
IN
Frequency select pin.
REF1
OUT
14.318 MHz reference clock.
11
REF2
OUT
14.318 MHz reference clock.
FS2
1, 3
IN
Frequency select pin.
PCICLK_F
OUT
Free running PCICLK not stoped by PCI_STOP#
21, 20, 19, 16, 15,
14
PCICLK(5:0)
OUT
PCI clock outputs.
MULTSEL
2, 3
IN
3.3V LVTTL input for selecting the current multiplier for CPU outputs.
24_48MHz
OUT
Selectable 48 or 24MHz output
FS3
2, 3
IN
Frequency select pin.
48MHz
OUT
48MHz output clock
26
SCLK
IN
Clock input of I
2
C input, 5V tolerant input
PD#
1
IN
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms. This pin
will be activiated when
VttPWRGD#
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS
and MULTISEL0 inputs are valid and are ready to be sampled (active low)
28
CPU_STOP#
1
IN
This asynchronous input halts CPU, SDRAM, and AGP clocks at logic "0" level
when driven low, the stop selection can be programmed through I
2
C.
29
PCI_STOP#
1
IN
Stops all PCICLKsbesides the PCICLK_F clocks at logic 0 level,
when input low
32, 33, 34, 35, 38,
39, 40, 41
SDRAM ( 7:0 )
OUT
SDRAM clock outputs.
42
SDRAM_STOP#
1
IN
Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level, when input
low
43
SDATA
IN
Data input for I
2
C serial input, 5V tolerant input
44
VDDL
PWR
Power supply pins, nominal 2.5V
45
CPUCLK
OUT
2.5V CPU clock
47
I REF
OUT
This pin establishes the reference current for the CPUCLK pairs. This
pin requires a fixed precision resistor tied to ground in order to establish
the appropriate current.
23
27
10
8
13
24
3
ICS950104
Advance Information
Third party brands and names are the property of their respective owners.
General Description
The ICS950104 is a main clock synthesizer chip for PIII based systems with ALI 1651 style chipset. This provides all clocks
required for such a system.
The ICS950104 belongs to ICS new generation of programmable system clock generators. It employs serial programming I
2
C
interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring
output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks.
This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system
become unstable from over clocking.
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4
ICS950104
Advance Information
Third party brands and names are the property of their respective owners.
General I
2
C serial interface information for the ICS950104
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending Byte 0 through Byte 20
(see Note)
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends Byte 0 through byte 8 (default)
ICS clock sends Byte 0 through byte X (if X
(H)
was
written to byte 8).
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
*See notes on the following page
.
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 18
ACK
Byte 19
ACK
Byte 20
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D3
(H )
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
If 7
H
has been written to B8
Byte 7
ACK
If 12
H
has been written to B8
Byte18
ACK
If 13
H
has been written to B8
Byte 19
ACK
If 14
H
has been written to B8
Byte 20
ACK
Stop Bit
How to Read:
5
ICS950104
Advance Information
Third party brands and names are the property of their respective owners.
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is
defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiver.
3.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4.
The input is operating at 3.3V logic levels.
5.
The data byte format is 8 bit bytes.
6.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
Notes:
Brief I
2
C registers description for ICS950104
Programmable System Frequency Generator
Register N ame
Byte
Description
PWD Default
Functionality & Frequency
Select Register
0
Output frequency, hardware / I
2
C
frequency select, spread spectrum &
output enable control register.
See individual
byte description
Output Control Registers
1-6
Active / inactive output control
registers/latch inputs read back.
See individual
byte description
Vendor ID & Revision ID
Registers
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
See individual
byte description
Byte Count
Read Back Register
8
Writing to this register will configure
byte count and how many byte w ill be
read back. Do not write 00
H
to this byte.
08
H
Watchdog Timer
Count Register
9
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
10
H
Watchdog Control Registers 10 Bit [6:0]
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
000,0000
VCO Control Selection Bit
10 Bit [7]
This bit select w hether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
0
VCO Frequency Control
Registers
11-12
These registers control the dividers ratio
into the phase detector and thus control
the V CO output frequency.
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
13-14
These registers control the spread
percentage amount.
Depended on
hardware/byte 0
configuration
Group Skews Control
Registers
15-16
Increment or decrement the group skew
amount as compared to the initial skew .
See individual
byte description
Output Rise/Fall Time
Select Registers
17-20
These registers will control the output
rise and fall time.
See individual
byte description
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