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Integrated
Circuit
Systems, Inc.
ICS950201
0460F--06/04/03
Block Diagram
Pin Configuration
56-Pin SSOP & TSSOP
Frequency Table
Recommended Application:
CK-408 clock for Intel
845 chipset with P4 processor.
Output Features:
3 Differential CPU Clock Pairs @ 3.3V
7 PCI (3.3V) @ 33.3MHz
3 PCI_F (3.3V) @ 33.3MHz
1 USB (3.3V) @ 48MHz
1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
5 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
Supports spread spectrum modulation,
down spread 0 to -0.5%.
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Uses external 14.318MHz crystal
Stop clocks and functional control available through
I
2
C interface.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps, programmable over 800 ps
with groups CPU0,1 and CPU2.
* These inputs have 150K internal pull-up resistor to VDD.
Programmable Timing Control HubTM for P4TM
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Integrated
Circuit
Systems, Inc.
ICS950201
0460F--06/04/03
Pin Description
Power Groups
(Analog)
(Digital)
VDDA = Analog Core PLL1
VDDPCI
VDDREF = REF, Xtal
VDD3V66
VDD48 = 48MHz, PLL
VDDCPU
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Integrated
Circuit
Systems, Inc.
ICS950201
0460F--06/04/03
Host Swing Select Functions
Maximum Allowed Current
Truth Table
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A
m
2
3
.
2
=
f
e
r
I
F
E
R
I
*
6
=
h
o
I
0
5
@
V
7
.
0
4
Integrated
Circuit
Systems, Inc.
ICS950201
0460F--06/04/03
Byte 0: Control Register
Byte 1: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the
system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP
functionality via I
2
C Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the I
2
C Byte 0 Bit3. In Software mode it is not allowed to pull the external
PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions.
The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these
modes.
In Hardware mode the I
2
C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in
PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I
2
C Byte 0 Bit 3 = 0)].
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC
off, and external resistor termination will bring CPUCLKC low.
t
i
B
#
n
i
P
e
m
a
N
D
W
P
2
e
p
y
T
1
n
o
i
t
p
i
r
c
s
e
D
0
t
i
B
4
5
0
S
F
X
R
n
o
d
e
l
p
m
a
s
n
i
p
0
S
F
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
p
u
r
e
w
o
p
1
t
i
B
5
5
1
S
F
X
R
n
o
d
e
l
p
m
a
s
n
i
p
1
S
F
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
p
u
r
e
w
o
p
2
t
i
B
0
4
2
S
F
X
R
n
o
d
e
l
p
m
a
s
n
i
p
2
S
F
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
p
u
r
e
w
o
p
3
t
i
B
4
3
#
P
O
T
S
_
I
C
P
3
X
R
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
:
e
d
o
m
e
r
a
w
d
r
a
H
D
W
P
n
o
d
e
l
p
m
a
s
n
i
p
#
P
O
T
S
_
I
C
P
1
W
R
:
e
d
o
m
e
r
a
w
t
f
o
S
d
e
p
p
o
t
s
K
L
C
I
C
P
=
0
d
e
p
p
o
t
s
t
o
n
K
L
C
I
C
P
=
1
4
t
i
B
3
5
#
P
O
T
S
_
U
P
C
X
R
l
a
n
r
e
t
x
e
e
h
t
f
o
e
u
l
a
v
t
n
e
r
r
u
c
e
h
t
s
t
c
e
l
f
e
R
n
i
p
#
P
O
T
S
_
U
P
C
5
t
i
B
5
3
H
C
V
/
1
_
6
6
V
3
0
W
R
z
H
M
8
4
/
z
H
M
6
6
t
c
e
l
e
S
H
C
V
z
H
M
8
4
=
1
,
z
H
M
6
6
=
0
6
t
i
B
-
0
)
d
e
v
r
e
s
e
R
(
7
t
i
B
-
d
a
e
r
p
S
d
e
l
b
a
n
E
0
W
R
n
O
d
a
e
r
p
S
=
1
,
f
f
O
d
a
e
r
p
S
=
0
t
i
B
#
n
i
P
e
m
a
N
D
W
P
2
e
p
y
T
1
n
o
i
t
p
i
r
c
s
e
D
0
t
i
B
1
5
,
2
5
0
T
K
L
C
U
P
C
0
C
K
L
C
U
P
C
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
4
1
t
i
B
8
4
,
9
4
1
T
K
L
C
U
P
C
1
C
K
L
C
U
P
C
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
4
2
t
i
B
4
4
,
5
4
2
T
K
L
C
U
P
C
2
C
K
L
C
U
P
C
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
4
3
t
i
B
1
5
,
2
5
0
T
K
L
C
U
P
C
0
C
K
L
C
U
P
C
0
W
R
n
o
i
t
r
e
s
s
a
h
t
i
w
0
C
/
0
T
K
L
C
U
P
C
f
o
l
o
r
t
n
o
c
w
o
ll
A
e
e
r
F
=
1
g
n
i
n
n
u
r
e
e
r
f
t
o
N
=
0
#
P
O
T
S
_
U
P
C
f
o
g
n
i
n
n
u
r
4
t
i
B
8
4
,
9
4
1
T
K
L
C
U
P
C
1
C
K
L
C
U
P
C
0
W
R
n
o
i
t
r
e
s
s
a
h
t
i
w
1
C
/
1
T
K
L
C
U
P
C
f
o
l
o
r
t
n
o
c
w
o
ll
A
e
e
r
F
=
1
g
n
i
n
n
u
r
e
e
r
f
t
o
N
=
0
#
P
O
T
S
_
U
P
C
f
o
g
n
i
n
n
u
r
5
t
i
B
4
4
,
5
4
2
T
K
L
C
U
P
C
2
C
K
L
C
U
P
C
0
W
R
n
o
i
t
r
e
s
s
a
h
t
i
w
2
C
/
2
T
K
L
C
U
P
C
f
o
l
o
r
t
n
o
c
w
o
ll
A
e
e
r
F
=
1
g
n
i
n
n
u
r
e
e
r
f
t
o
N
=
0
#
P
O
T
S
_
U
P
C
f
o
g
n
i
n
n
u
r
6
t
i
B
-
-
0
-
)
d
e
v
r
e
s
e
R
(
7
t
i
B
3
4
0
L
E
S
T
L
U
M
X
R
0
L
E
S
T
L
U
M
f
o
e
u
l
a
v
t
n
e
r
r
u
c
e
h
t
s
t
c
e
l
f
e
R
5
Integrated
Circuit
Systems, Inc.
ICS950201
0460F--06/04/03
Byte 2: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
Byte 3: Control Register
Byte 4: Control Register
t
i
B
#
n
i
P
e
m
a
N
D
W
P
e
p
y
T
n
o
i
t
p
i
r
c
s
e
D
0
t
i
B
0
1
0
K
L
C
I
C
P
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
1
t
i
B
1
1
1
K
L
C
I
C
P
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
2
t
i
B
2
1
2
K
L
C
I
C
P
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
3
t
i
B
3
1
3
K
L
C
I
C
P
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
4
t
i
B
6
1
4
K
L
C
I
C
P
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
5
t
i
B
7
1
5
K
L
C
I
C
P
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
6
t
i
B
8
1
6
K
L
C
I
C
P
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
7
t
i
B
-
-
0
-
)
d
e
v
r
e
s
e
R
(
t
i
B
#
n
i
P
e
m
a
N
D
W
P
e
p
y
T
n
o
i
t
p
i
r
c
s
e
D
0
t
i
B
5
0
F
_
K
L
C
I
C
P
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
1
t
i
B
6
1
F
_
K
L
C
I
C
P
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
2
t
i
B
7
2
F
_
K
L
C
I
C
P
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
3
t
i
B
5
0
F
_
K
L
C
I
C
P
0
W
R
f
o
n
o
i
t
r
e
s
s
a
h
t
i
w
0
F
_
K
L
C
I
C
P
f
o
l
o
r
t
n
o
c
w
o
ll
A
e
e
r
f
t
o
N
=
1
,
g
n
i
n
n
u
R
e
e
r
F
=
0
.
#
P
O
T
S
_
I
C
P
g
n
i
n
n
u
r
4
t
i
B
6
1
F
_
K
L
C
I
C
P
0
W
R
f
o
n
o
i
t
r
e
s
s
a
h
t
i
w
1
F
_
K
L
C
I
C
P
f
o
l
o
r
t
n
o
c
w
o
ll
A
e
e
r
f
t
o
N
=
1
,
g
n
i
n
n
u
R
e
e
r
F
=
0
.
#
P
O
T
S
_
I
C
P
g
n
i
n
n
u
r
5
t
i
B
7
2
F
_
K
L
C
I
C
P
0
W
R
f
o
n
o
i
t
r
e
s
s
a
h
t
i
w
2
F
_
K
L
C
I
C
P
f
o
l
o
r
t
n
o
c
w
o
ll
A
e
e
r
f
t
o
N
=
1
,
g
n
i
n
n
u
R
e
e
r
F
=
0
.
#
P
O
T
S
_
I
C
P
g
n
i
n
n
u
r
6
t
i
B
9
3
B
S
U
_
z
H
M
8
4
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
7
t
i
B
8
3
T
O
D
_
z
H
M
8
4
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
t
i
B
#
n
i
P
e
m
a
N
D
W
P
e
p
y
T
n
o
i
t
p
i
r
c
s
e
D
0
t
i
B
1
2
2
-
6
6
V
3
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
1
t
i
B
2
2
3
-
6
6
V
3
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
2
t
i
B
3
2
4
-
6
6
V
3
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
3
t
i
B
4
2
5
_
6
6
V
3
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
4
t
i
B
5
3
K
L
C
_
H
C
V
/
1
_
6
6
V
3
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
5
t
i
B
3
3
0
_
6
6
V
3
1
W
R
d
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
6
t
i
B
-
-
0
R
)
d
e
v
r
e
s
e
R
(
7
t
i
B
-
-
0
R
)
d
e
v
r
e
s
e
R
(