Integrated
Circuit
Systems, Inc.
ICS950401
0499C--11/01/04
Block Diagram
Functionality
Pin Configuration
Recommended Application:
AMD K8 Systems
Output Features:
2 - Differential pair push-pull CPU clocks @ 3.3V
7 - PCI (Including 1 free running) @3.3V
3 - Selectable HT/PCI 66/33MHz @3.3V
1 - 48MHz, @3.3V fixed.
1 - 24/48MHz @ 3.3V
3 - REF @3.3V, 14.318MHz.
Features:
Up to 220MHz frequency support
Support power management: PCI stop and stop
clocks controlled by I
2
C.
Spread spectrum for EMI reduction
Uses external 14.318MHz crystal
I
2
C programmability features
Supports Hypes transport technology (HT66 output).
AMD - K8
TM System Clock Chip
*FS0/REF0 1
48 REF1/FS1*
VDDREF 2
47 GND
X1 3
46 VDDREF
X2 4
45 REF2/FS2*
GND 5
44 SPREAD*
*PCI33/HT66SEL# 6
43 VDDA
PCICLK33/HT66_0 7
42 GNDA
PCICLK33/HT66_1 8
41 CPUCLKT0
VDDPCI 9
40 CPUCLKC0
GND 10
39 GND
PCICLK33/HT66_2 11
38 VDDCPU
NC 12
37 CPUCLKT1
PCICLK0 13
36 CPUCLKC1
PCICLK1 14
35 VDD
GND 15
34 GND
VDDPCI 16
33 GNDA
PCICLK2 17
32 VDDA
PCICLK3 18
31 48MHz
VDDPCI 19
30 GND
GND 20
29 VDD
PCICLK4 21
28 24_48MHz/Sel24_48#*
PCICLK5 22
27 GND
PCICLK_F 23
26 SDATA
*PCI_STOP# 24
25 SCLK
48-SSOP/ TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
I
C
S
950401
FS2 FS1 FS0
PCI33_HT66
SEL#
CPU
PCI33
PCI33_HT66
COMMENTS
0
0
0
X
Hi-Z
Hi-Z
Hi-Z
Tri-State Mode
0
0
1
0
X
X/6
X/3
Bypass Mode
0
0
1
1
X
X/6
X/6
Bypass Mode
0
1
0
X
180.00
30.00
60.00
10% under-clk
0
1
1
X
220.00
36.56
73.12
10% over-clk
1
0
0
X
100.00
33.33
33.33/66.66
Athlon Compatible
1
0
1
X
133.33
33.33
33.33/66.66
Athlon Compatible
1
1
0
X
166.66
33.33
33.33/66.66
Reserved
1
1
1
X
200.00
33.33
33.33/66.66
Hammer Operation
PLL2
PLL1
Spread
Spectrum
PCICLK (5:0)
CPUCLKT (1:0)
CPUCLKC (1:0)
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
Stop
SDATA
SCLK
FS (2:0)
SPREAD
24_48SEL#
PCI33/HT66SEL#
PCI_STOP#
Control
Logic
REF (2:0)
48MHz
24_48MHz
/ 2
PCICLK_F
PCICLK33/HT66(2:0)
X 2
Config.
Reg.
2
ICS950401
0499C--11/01/04
Pin Descriptions
PIN
PIN
PIN
#
NAME
TYPE
1
*FS0/REF0
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
2
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
3
X1
IN
Crystal input, Nominally 14.318MHz.
4
X2
OUT
Crystal output, Nominally 14.318MHz
5
GND
PWR
Ground pin.
6
*PCI33/HT66SEL#
IN
Input for PCI33/HT66 select. 0= 66.66MHz, 1= 33.33MHz,
7
PCICLK33/HT66_0
IN
PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
8
PCICLK33/HT66_1
IN
PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
9
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
10
GND
PWR
Ground pin.
11
PCICLK33/HT66_2
IN
PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
12
NC
NC
No Connect
13
PCICLK0
OUT
PCI clock output.
14
PCICLK1
OUT
PCI clock output.
15
GND
PWR
Ground pin.
16
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
17
PCICLK2
OUT
PCI clock output.
18
PCICLK3
OUT
PCI clock output.
19
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
20
GND
PWR
Ground pin.
21
PCICLK4
OUT
PCI clock output.
22
PCICLK5
OUT
PCI clock output.
23
PCICLK_F
I/O
Free running PCI clock not affected by PCI_STOP# / Mode selection latch input pin.
24
*PCI_STOP#
I/O
Input select pin, Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
input low.
25
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
26
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
27
GND
PWR
Ground pin.
28
24_48MHz/Sel24_48#*
I/O
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =
24MHz.
29
VDD
PWR
Power supply, nominal 3.3V
30
GND
PWR
Ground pin.
31
48MHz
OUT
48MHz clock output.
32
VDDA
PWR
3.3V power for the PLL core.
33
GNDA
PWR
Ground pin for the PLL core.
34
GND
PWR
Ground pin.
35
VDD
PWR
Power supply, nominal 3.3V
36
CPUCLKC1
OUT
Complementory clock of differential CPU outputs. Push-pull requires external
termination.
37
CPUCLKT1
OUT
True clock of differential CPU outputs. Push-pull requires external termination.
38
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
39
GND
PWR
Ground pin.
40
CPUCLKC0
OUT
Complementory clock of differential CPU outputs. Push-pull requires external
termination.
41
CPUCLKT0
OUT
True clock of differential CPU outputs. Push-pull requires external termination.
42
GNDA
PWR
Ground pin for the PLL core.
43
VDDA
PWR
3.3V power for the PLL core.
44
SPREAD*
IN
Asynchronous, active high input, with internal 120Kohm pull-up resistor, to enable
spread spectrum functionality.
45
REF2/FS2*
I/O
14.318 MHz reference clock / Frequency select latch input pin.
46
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
47
GND
PWR
Ground pin.
48
REF1/FS1*
I/O
14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength
DESCRIPTION
3
ICS950401
0499C--11/01/04
General Description
The ICS950401 is a main clock synthesizer chip for AMD-K8. This provides all clocks required for Clawhammer and
Sledgehammer systems.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS950401
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDDA = PLL2
Pin 32
VDDA = VDD for Core PLL
Pin 43
VDDREF = REF, Xtal
Pin 2
Skew Characteristics
Parameter
Description
Test Conditons
Skew
Window
Unit
T
sk_CPU_CPU
measured at x-ing of CPU,
250
ps
T
sk_CPU_PCI
measured at x-ing of CPU,
1.5V of PCI clock
2000
ps
T
sk_PCI_PCI
measured between rising
edge at 1.5V
500
ps
T
sk_PCI33-HT66
measured between rising
edge at 1.5V
500
ps
T
sk_CPU_HT66
measured between rising
edge at 1.5V
2000
ps
T
sk_CPU_HT66
measured at x-ing of CPU,
1.5V of PCI clock
500
ps
T
sk_CPU_CPU
measured at x-ing of CPU,
200
ps
T
sk_CPU_PCI
measured at x-ing of CPU,
1.5V of PCI clock
200
ps
T
sk_PCI_PCI
measured between rising
edge at 1.5V
200
ps
T
sk_PCI33-HT66
measured between rising
edge at 1.5V
200
ps
T
sk_CPU_HT66
measured between rising
edge at 1.5V
200
ps
T
sk_CPU_HT66
measured at x-ing of CPU,
1.5V of PCI clock
200
ps
time independent
skew
not dependent on
V, T changes
time variant skew
varies over
V, T changes
4
ICS950401
0499C--11/01/04
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byt
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byt
e
ACK
ACK
5
ICS950401
0499C--11/01/04
Byte0: Functionality and Frequency Select
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3
Notes:
1. Write Disable. A '1' written to this bit after a '1' is written to BYTE0/bit 0 will permanently disable writing to I2C until
the part is powered off. Once the clock generator has been write disabled, the SMBus controller should still accept and
acknowledge subsequent write cycles but it should not modify any of the registers.
2.
3. A '1' written to this bit after power-up will enable writing to I2C. Subsequent '0's written to this bit will disable
modification of all registers except this single bit. When a '1' is written to Byte 0 Bit 7, all modification is permanently
disabled until the device power cycles. Block write transactions to the interface will complete, however unless the
interface has been previously unlocked, the writes will have no effect. The effect of writing to this bit does not take effect
until the subsequent block write command.
4. Clarification on frequency select on power-up:
i. Upon power-up, Byte0, bits (5:1) [FS(4:0)] are set to default hardware settings.
ii. A '1' is written to Byte0, bit 0 to enable software control.
iii. Every time Byte0 is written, frequency input defaults will be affected.
iv. If a '0' is written to Byte0, bit0, the software control is disabled. Disabling software control does not cause the
contents of Byte0
to default back to hardware setting for FS(4:0).
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