Integrated
Circuit
Systems, Inc.
ICS950402
0700B--04/30/04
Block Diagram
Functionality
Pin Configuration
Recommended Application:
AMD K8 System Clock with AMD or VIA Chipset
Output Features:
2 - Differential pair push-pull CPU clocks @
3.3V
9 - PCICLK (Including 1 free running) @3.3V
4 - Selectable PCICLK/HTTCLK @3.3V
1 - 48MHz, @3.3V fixed.
1 - 24/48MHz @ 3.3V
3 - REF @3.3V, 14.318MHz.
Features:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI
control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/
write operations.
Uses external 14.318MHz crystal.
Supports Hyper Transport Technology (HTTCLK).
AMD - K8TM System Clock Chip
PLL2
PLL1
Spread
Spectrum
PCICLK (6:0, 11)
CPUCLKT (1:0)
CPUCLKC (1:0)
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
Stop
SDATA
SCLK
FS (3:0)
24_48SEL#
MODE (A,B,C)
PCI_STOP#
Control
Logic
REF (2:0)
48MHz
24_48MHz
/ 2
PCICLK_F
PCICLK/HTTCLK (3:0)
X 2
Config.
Reg.
CPU
HTT
PCI
MHz
MHz
MHz
0
0
0
0
100.90
67.27
33.63
0
0
0
1
133.90
66.95
33.48
0
0
1
0
168.00
67.20
33.60
0
0
1
1
202.00
67.33
33.67
0
1
0
0
100.20
66.80
33.40
0
1
0
1
133.50
66.75
33.38
0
1
1
0
166.70
66.68
33.34
0
1
1
1
200.40
66.80
33.40
1
0
0
0
150.00
60.00
30.00
1
0
0
1
180.00
60.00
30.00
1
0
1
0
210.00
70.00
35.00
1
0
1
1
240.00
60.00
30.00
1
1
0
0
270.00
67.50
33.75
1
1
0
1
233.33
66.67
33.33
1
1
1
0
266.67
66.67
33.33
1
1
1
1
300.00
75.00
37.50
FS3
FS2
FS1
FS0
*FS0/REF0 1
48 REF1/FS1*
VDDREF 2
47 GND
X1 3
46 VDDREF
X2 4
45 REF2/FS2*
GND 5
44 Reset#
*(PCICLK7/HTTCLK0)ModeA 6
43 VDDA
*PCICLK8/HTTCLK1/ModeB 7
42 GND
PCICLK9/HTTCLK2 8
41 CPUCLK8T0
VDDPCI 9
40 CPUCLK8C0
GND 10
39 GND
PCICLK10/HTTCLK3 11
38 VDDCPU
PCICLK11 12
37 CPUCLK8T1
PCICLK0 13
36 CPUCLK8C1
PCICLK1 14
35 VDDCPU
GND 15
34 GND
VDDPCI 16
33 GND
****PCICLK2 17
32 VDD
****PCICLK3 18
31 48MHz/FS3**
VDDPCI 19
30 GND
GND 20
29 AVDD48
PCICLK4 21
28 24_48MHz/Sel24_48#*~
PCICLK5 22
27 GND
~*PCICLK_F/ModeC 23
26 SDATA
~*(PCICLK6)PCI_STOP# 24
25 SCLK
48-Pin TSSOP/SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This Output has 2X Drive Strength
**** This Output has 2.3X Drive Strength
I
C
S
9
50
40
2
2
ICS950402
0700B--04/30/04
Pin Descriptions
PIN #
PIN NAME
PIN
TYPE
DESCRIPTION
1
*FS0/REF0
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
2
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
3
X1
IN
Crystal input, Nominally 14.318MHz.
4
X2
OUT
Crystal output, Nominally 14.318MHz
5
GND
PWR
Ground pin.
6
*(PCICLK7/HTTCLK0)ModeA
I/O
PCI clock output / Hyper Transport output / Mode selection pin, this input is activated by the
ModeB selection pin.
7
*PCICLK8/HTTCLK1/ModeB
I/O
PCI clock output / Hyper Transport output / Mode selection latch input pin.
8
PCICLK9/HTTCLK2
OUT
PCI clock output / Hyper Transport output.
9
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
10
GND
PWR
Ground pin.
11
~PCICLK10/HTTCLK3
OUT
PCI clock output / Hyper Transport output.
12
PCICLK11
OUT
PCI clock output.
13
PCICLK0
OUT
PCI clock output.
14
PCICLK1
OUT
PCI clock output.
15
GND
PWR
Ground pin.
16
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
17
****PCICLK2
OUT
Real time system reset signal for watchdog timer timeout. This signal is active low and
selected by Mode latch input / 3.3V PCI clock clock output.
18
****PCICLK3
I/O
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low / PCI clock
output, this output is activated by the Mode selection pin
19
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
20
GND
PWR
Ground pin.
21
PCICLK4
OUT
PCI clock output.
22
PCICLK5
OUT
PCI clock output.
23
~*PCICLK_F/ModeC
I/O
Free running PCI clock not affected by PCI_STOP# / Mode selection latch input pin.
24
~*(PCICLK6)PCI_STOP#
I/O
PCI clock output, this output is activated by the Mode selection pin / Stops all PCICLKs
besides the PCICLK_F clocks at logic 0 level, when input low.
25
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
26
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
27
GND
PWR
Ground pin.
28
24_48MHz/Sel24_48#*~
I/O
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz.
29
AVDD48
PWR
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
30
GND
PWR
Ground pin.
31
48MHz/FS3**
I/O
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
32
VDD
PWR
Power supply, nominal 3.3V
33
GND
PWR
Ground pin.
34
GND
PWR
Ground pin.
35
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
36
CPUCLK8C1
OUT
"Complimentary" clocks of differential 3.3V push-pull K8 pair.
37
CPUCLK8T1
OUT
"True" clocks of differential 3.3V push-pull K8 pair.
38
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
39
GND
PWR
Ground pin.
40
CPUCLK8C0
OUT
"Complimentary" clocks of differential 3.3V push-pull K8 pair.
41
CPUCLK8T0
OUT
"True" clocks of differential 3.3V push-pull K8 pair.
42
GND
PWR
Ground pin.
43
VDDA
PWR
3.3V power for the PLL core.
44
Reset#
OUT
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
45
REF2/FS2*
I/O
14.318 MHz reference clock / Frequency select latch input pin.
46
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
47
GND
PWR
Ground pin.
48
REF1/FS1*
I/O
14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength
**** This Output has 2.3X Drive Strength
3
ICS950402
0700B--04/30/04
General Description
The ICS950402 is a main system clock solution for desktop designs using the AMD K8 CPU. It provides all necessary
clock signals for Clawhammer and Sledgehammer systems.
The ICS950402 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This
part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the
use of a serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency
setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and
enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to
0.1MHz increment.
Power Groups
AVDD
GND
2
5
Crystal
29
27, 30
48MHz fixed,
32
33
Fix Analog, Fix Digital
43
42
CPU Master Clock, CPU Analog
VDD
GND
9
10
PCI33_HT66outputs
16, 19
15, 20
PCI33 outputs
35, 38
34, 39
CPU outputs
46
47
REF
Pin Number
Description
Mode Functionality Tables
ModeA
ModeB
Pin6
Pin7
Pin8
Pin11
0
0
HTTCLK0
HTTCLK1
HTTCLK2
PCICLK10
0
1
ModeA
(Input Only)
HTTCLK1
HTTCLK2
HTTCLK3
1
0
PCICLK7
PCICLK8
PCICLK9
PCICLK10
1
1
ModeA
(Input Only)
PCICLK8
PCICLK9
PCICLK10
ModeC
Pin24
0
PCICLK6
1
PCI_STOP#
4
ICS950402
0700B--04/30/04
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byt
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byt
e
ACK
ACK
5
ICS950402
0700B--04/30/04
Table1: Frequency Selection Table
Bit4
Bit3
Bit2
Bit1
CPU
HTT
PCI
VCO
FS3
FS2
FS1
FS0
MHz
MHz
MHz
MHz
0
0
0
0
0
100.90
67.27
33.63
403.60
0
0
0
0
1
133.90
66.95
33.48
535.60
0
0
0
1
0
168.00
67.20
33.60
672.00
0
0
0
1
1
202.00
67.33
33.67
404.00
0
0
1
0
0
100.20
66.80
33.40
400.80
0
0
1
0
1
133.50
66.75
33.38
534.00
0
0
1
1
0
166.70
66.68
33.34
666.80
0
0
1
1
1
200.40
66.80
33.40
400.80
0
1
0
0
0
150.00
60.00
30.00
600.00
0
1
0
0
1
180.00
60.00
30.00
360.00
0
1
0
1
0
210.00
70.00
35.00
420.00
0
1
0
1
1
240.00
60.00
30.00
480.00
0
1
1
0
0
270.00
67.50
33.75
540.00
0
1
1
0
1
233.33
66.67
33.33
466.66
0
1
1
1
0
266.67
66.67
33.33
533.34
0
1
1
1
1
300.00
75.00
37.50
600.00
1
0
0
0
0
100.00
66.67
33.33
400.00
1
0
0
0
1
133.33
66.67
33.33
533.32
1
0
0
1
0
166.66
66.66
33.33
666.64
1
0
0
1
1
200.00
66.67
33.33
400.00
1
0
1
0
0
103.00
68.67
34.33
412.00
1
0
1
0
1
137.33
68.66
34.33
549.32
1
0
1
1
0
171.66
68.66
34.33
686.64
1
0
1
1
1
206.00
68.67
34.33
412.00
1
1
0
0
0
154.50
61.80
30.90
618.00
1
1
0
0
1
185.40
61.80
30.90
370.80
1
1
0
1
0
216.30
72.10
36.05
432.60
1
1
0
1
1
247.20
61.80
30.90
494.40
1
1
1
0
0
278.10
69.53
34.76
556.20
1
1
1
0
1
240.33
68.67
34.33
480.66
1
1
1
1
0
274.67
68.67
34.33
549.34
1
1
1
1
1
309.00
77.25
38.63
618.00
Bit5
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