Integrated
Circuit
Systems, Inc.
ICS950405
0802F--04/22/05
Functionality
Recommended Application:
AMD K8 System Clock with AMD, VIA or ALI Chipset
Output Features:
2 - Differential pair push-pull CPU clocks @
3.3V
9 - PCICLK (Including 1 free running) @ 3.3V
3 - Selectable PCICLK/HTTCLK @ 3.3V
1 - HTTCLK @ 3.3V
1 - 48MHz @ 3.3V fixed.
1 - 24/48MHz @ 3.3V
3 - REF @ 3.3V, 14.318MHz.
AMD - K8
TM
System Clock Chip
CPU
HTT
PCI
MHz
MHz
MHz
0
0
0
0
100.90
67.27
33.63
0
0
0
1
133.90
66.95
33.48
0
0
1
0
168.00
67.20
33.60
0
0
1
1
202.00
67.33
33.67
0
1
0
0
100.20
66.80
33.40
0
1
0
1
133.50
66.75
33.38
0
1
1
0
166.70
66.68
33.34
0
1
1
1
200.40
66.80
33.40
1
0
0
0
150.00
60.00
30.00
1
0
0
1
180.00
60.00
30.00
1
0
1
0
210.00
70.00
35.00
1
0
1
1
240.00
60.00
30.00
1
1
0
0
270.00
67.50
33.75
1
1
0
1
233.33
66.67
33.33
1
1
1
0
266.67
66.67
33.33
1
1
1
1
300.00
75.00
37.50
FS0
FS3
FS2
FS1
Pin Configuration
*FS0/REF0 1
48 REF1/FS1*
VDDHTT 2
47 GND
X1 3
46 VDDREF
X2 4
45 REF2/FS2*
GND 5
44 Reset#
*ModeA/HTTCLK0 6
43 VDDA
*ModeB/PCICLK8/HTTCLK1 7
42 GND
PCICLK9/HTTCLK2 8
41 CPUCLK8T0
VDDPCI 9
40 CPUCLK8C0
GND 10
39 GND
PCICLK11/HTTCLK3 11
38 VDDCPU
PCICLK10 12
37 CPUCLK8T1
PCICLK0 13
36 CPUCLK8C1
PCICLK1 14
35 VDDCPU
GND 15
34 GND
VDDPCI 16
33 GND
PCICLK2 17
32 PD#*
PCICLK3 18
31 48MHz/FS3**
VDDPCI 19
30 GND
GND 20
29 AVDD48
2X
PCICLK4 21
28 24_48MHz/Sel24_48#*
2X
PCICLK5 22
27 GND
2X
PCICLK6 23
26 SDATA
2X
PCICLK7 24
25 SCLK
48-SSOP
* Internal Pull-Up Resistor
IC
S9
50
405
2X
This Output has 2X Default Drive and can be programmaed lower via IIC
Features:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology and RESET# output to
reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/write
operations.
Uses external 14.318MHz crystal.
Supports Hyper Transport Technology (HTTCLK).
2
ICS950405
0802F--04/22/05
Pin Descriptions
PIN # PIN NAME
PIN
TYPE
DESCRIPTION
1
*FS0/REF0
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
2
VDDHTT
PWR
Supply for HTT clocks, nominal 3.3V.
3
X1
IN
Crystal input, Nominally 14.318MHz.
4
X2
OUT
Crystal output, Nominally 14.318MHz
5
GND
PWR
Ground pin.
6
*ModeA/HTTCLK0
I/O
Mode selection latch input pin / Hyper Transport output.
7
*ModeB/PCICLK8/HTTCLK1
I/O
Mode selection latch input pin / PCI clock output / Hyper Transport output.
8
PCICLK9/HTTCLK2
OUT
PCI clock output / Hyper Transport output.
9
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
10
GND
PWR
Ground pin.
11
PCICLK11/HTTCLK3
I/O
PCI clock output / Hyper Transport output.
12
PCICLK10
OUT
PCI clock output.
13
PCICLK0
OUT
PCI clock output.
14
PCICLK1
OUT
PCI clock output.
15
GND
PWR
Ground pin.
16
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
17
PCICLK2
OUT
PCI clock output.
18
PCICLK3
OUT
PCI clock output.
19
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
20
GND
PWR
Ground pin.
21
2XPCICLK4
OUT
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
22
2XPCICLK5
OUT
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
23
2XPCICLK6
OUT
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
24
2XPCICLK7
OUT
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
25
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
26
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
27
GND
PWR
Ground pin.
28
24_48MHz/Sel24_48#*
I/O
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz.
29
AVDD48
PWR
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
30
GND
PWR
Ground pin.
31
48MHz/FS3**
I/O
Fixed 48MHz clock output. 3.3V / 'Frequency select latch input pin
32
PD#*
IN
Asynchronous active low input pin used to power down the device into a low power state.
The internal clocks are disabled and the VCO and the crystal are stopped.
33
GND
PWR
Ground pin.
34
GND
PWR
Ground pin.
35
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
36
CPUCLK8C1
OUT
Complimentary clock of differential 3.3V push-pull K8 pair.
37
CPUCLK8T1
OUT
True clock of differential 3.3V push-pull K8 pair.
38
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
39
GND
PWR
Ground pin.
40
CPUCLK8C0
OUT
Complimentary clock of differential 3.3V push-pull K8 pair.
41
CPUCLK8T0
OUT
True clock of differential 3.3V push-pull K8 pair.
42
GND
PWR
Ground pin.
43
VDDA
PWR
3.3V power for the PLL core.
44
Reset#
OUT
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
45
REF2/FS2*
I/O
14.318 MHz reference clock / Frequency select latch input pin.
46
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
47
GND
PWR
Ground pin.
48
REF1/FS1*
I/O
14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength
3
ICS950405
0802F--04/22/05
General Description
The ICS950405 is a main system clock solution for desktop designs using the AMD K8 CPU. It provides all necessary
clock signals for Clawhammer and Sledgehammer with AMD, VIA or ALI systems.
The ICS950405 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This
part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the
use of a serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency
setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and
enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to
0.1MHz increment.
Block Diagram
PLL2
PLL1
Spread
Spectrum
PCICLK (7:0, 10)
CPUCLKT (1:0)
CPUCLKC (1:0)
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
HTT
DIVDER
SDATA
SCLK
PD#
FS (3:0)
SEL24_48#
MODE (A,B)
Control
Logic
REF (2:0)
48MHz
24_48MHz
/ 2
PCICLK(11,9,8)/HTTCLK (3:1)
HTTCLK0
Config.
Reg.
4
ICS950405
0802F--04/22/05
Power Groups
VDD
GND
2
5
Xtal, POR
9
10
PCICLK, HTTCLK O/p
16,19
15,20
PCICLK Outputs
29
27,30,33
48 MHz, Fix Analog
35,38
34,39
CPU Outputs
43
42
Analog, CPU PLL, MCLK
46
47
REF, Digital Core
Pin Number
Description
Mode Functionality Tables
ModeA
ModeB
Pin7
Pin8
Pin11
0
0
HTTCLK1
HTTCLK2
PCICLK11
0
1
HTTCLK1
HTTCLK2
HTTCLK3
1
0
PCICLK8
PCICLK9
PCICLK11
1
1
HTTCLK1
PCICLK9
PCICLK11
Table1: Frequency Selection Table
Bit3
Bit2
Bit1
Bit0
CPU
HTT
PCI
FS3
FS2
FS1
FS0
MHz
MHz
MHz
0
0
0
0
100.90
67.27
33.63
0
0
0
1
133.90
66.95
33.48
0
0
1
0
168.00
67.20
33.60
0
0
1
1
202.00
67.33
33.67
0
1
0
0
100.20
66.80
33.40
0
1
0
1
133.50
66.75
33.38
0
1
1
0
166.70
66.68
33.34
0
1
1
1
200.40
66.80
33.40
1
0
0
0
150.00
60.00
30.00
1
0
0
1
180.00
60.00
30.00
1
0
1
0
210.00
70.00
35.00
1
0
1
1
240.00
60.00
30.00
1
1
0
0
270.00
67.50
33.75
1
1
0
1
233.33
66.67
33.33
1
1
1
0
266.67
66.67
33.33
1
1
1
1
300.00
75.00
37.50
5
ICS950405
0802F--04/22/05
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byt
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byt
e
ACK
ACK
6
ICS950405
0802F--04/22/05
I
2
C Table: Frequency Select Register
Bit 7
SS_EN
Spread Enable
RW
1
Bit 6
SEL24_48MHz
Output Select
RW
Latch
Bit 5
Reserved
Reserved
RW
X
Bit 4
Reserved
Reserved
RW
X
Bit 3
FS3
Freq Select Bit 3
RW
Latch
Bit 2
FS2
Freq Select Bit 2
RW
Latch
Bit 1
FS1
Freq Select Bit 1
RW
Latch
Bit 0
FS0
Freq Select Bit 0
RW
Latch
I
2
C Table: Output Control Register
Bit 7
REF0
Output Control
RW
1
Bit 6
HTTCLK0
Output Control
RW
1
Bit 5
PCICLK8/HTTCLK1
Output Control
RW
1
Bit 4
PCICLK9/HTTCLK2
Output Control
RW
1
Bit 3
PCICLK11/HTTCLK3
Output Control
RW
1
Bit 2
PCICLK10
Output Control
RW
1
Bit 1
PCICLK0
Output Control
RW
1
Bit 0
PCICLK1
Output Control
RW
1
I
2
C Table: Output Control Register
Bit 7
PCICLK2
Output Control
RW
1
Bit 6
PCICLK3
Output Control
RW
1
Bit 5
PCICLK4
Output Control
RW
1
Bit 4
PCICLK5
Output Control
RW
1
Bit 3
PCICLK6
Output Control
RW
1
Bit 2
PCICLK7
Output Control
RW
1
Bit 1
24_48MHz
Output Control
RW
1
Bit 0
48MHz
Output Control
RW
1
I
2
C Table: Output Control Register
Bit 7
CPUCLK8T/C_1
Output Control
RW
1
Bit 6
CPUCLK8T/C_0
Output Control
RW
1
Bit 5
REF2
Output Control
RW
1
Bit 4
REF1
Output Control
RW
1
Bit 3
PCI_Str1
RW
0
Bit 2
PCI_Str0
RW
1
Bit 1
PCI_Str1
RW
0
Bit 0
PCI_Str0
RW
1
PCI9,8 Strength
Control only
PCI11 Strength Control
only
-
00: 0.5X Drive
10: 1.5X Drive
-
01: 1.0X Drive
11: 2.0X Drive
-
00: 0.5X Drive
10: 1.5X Drive
-
01: 1.0X Drive
11: 2.0X Drive
45
Disable Enable
48
Disable
Enable
37,36
Disable Enable
41,40
Disable Enable
Type
0
1
PWD
Byte 3
Pin #
Name
Control Function
28
Disable
Enable
31
Disable
Enable
23
Disable
Enable
24
Disable
Enable
21
Disable Enable
22
Disable
Enable
17
Disable Enable
18
Disable Enable
Type
0
1
PWD
Byte 2
Pin #
Name
Control Function
13
Disable
Enable
14
Disable
Enable
11
Disable
Enable
12
Disable
Enable
7
Disable Enable
8
Disable
Enable
1
Disable Enable
6
Disable Enable
Type
0
1
PWD
Byte 1
Pin #
Name
Control Function
-
-
Reserved
Reserved
-
Reserved
Reserved
See Table1: Frequency Selection Table
-
-
-
Type
0
1
-
OFF
ON
-
48MHz
24MHz
PWD
Byte 0
Pin #
Name
Control Function
7
ICS950405
0802F--04/22/05
I
2
C Table: Output Control Register
Bit 7
PCIStr1
RW
0
Bit 6
PCIStr0
RW
1
Bit 5
PCIStr1
RW
1
Bit 4
PCIStr0
RW
1
Bit 3
PCIStr1
RW
1
Bit 2
PCIStr0
RW
1
Bit 1
PCIStr1
RW
1
Bit 0
PCIStr0
RW
1
I
2
C Table: Reserved Register
Bit 7
Reserved
Reserved
RW
X
Bit 6
Reserved
Reserved
RW
X
Bit 5
Reserved
Reserved
RW
X
Bit 4
Reserved
Reserved
RW
X
Bit 3
Reserved
Reserved
RW
X
Bit 2
Reserved
Reserved
RW
X
Bit 1
Reserved
Reserved
RW
X
Bit 0
Reserved
Reserved
RW
X
I
2
C Table: Byte Count Register
Bit 7
BC7
RW
0
Bit 6
BC6
RW
0
Bit 5
BC5
RW
0
Bit 4
BC4
RW
0
Bit 3
BC3
RW
0
Bit 2
BC2
RW
1
Bit 1
BC1
RW
1
Bit 0
BC0
RW
0
I
2
C Table: Byte Count and Vendor ID Register
Bit 7
REV_ID3
RW
0
Bit 6
REV_ID2
RW
0
Bit 5
REV_ID1
RW
0
Bit 4
REV_ID0
RW
0
Bit 3
Vendor_ID3
RW
0
Bit 2
Vendor_ID2
RW
0
Bit 1
Vendor_ID1
RW
0
Bit 0
Vendor_ID0
RW
1
PCICLK (5) Strength
Control
PCICLK (4) Strength
Control
Byte Count
Programming b(7:0)
Writing to this register will configure how
many bytes will be read back, default is
06 = 6 bytes.
Reserved
Reserved
Reserved
Reserved
All other PCICLK
Strength Control
PCICLK (7:6) Strength
Control
Reserved
Reserved
Reserved
Type
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
-
Vendor ID
-
-
-
-
-
-
-
-
-
-
-
-
Revision ID
-
-
-
-
-
-
Type
0
1
PWD
Byte 7
Pin #
Name
Control Function
-
-
Reserved
Reserved
-
-
-
-
-
-
Type
0
1
PWD
Byte 6
Pin #
Name
Control Function
-
-
-
-
-
-
-
-
PWD
Byte 5
Pin #
Name
Control Function
-
-
-
-
-
-
-
-
Type
0
1
PWD
Byte 4
Pin #
Name
Control Function
00: 0.5X Drive
10: 1.5X Drive
01: 1.0X Drive
11: 2.0X Drive
00: 0.5X Drive
10: 1.5X Drive
01: 1.0X Drive
11: 2.0X Drive
00: 0.5X Drive
01: 1.0X Drive
11: 2.0X Drive
10: 1.5X Drive
01: 1.0X Drive
11: 2.0X Drive
00: 0.5X Drive
10: 1.5X Drive
8
ICS950405
0802F--04/22/05
I
2
C Table: Skew Control Register
Bit 7
PCI/HTTSkw3
RW
0000:0
0100:150 1000:300 1100:450
1
Bit 6
PCI/HTTSkw2
RW
0001:N/A 0101:N/A 1001:N/A 1101:600
1
Bit 5
PCI/HTTSkw1
RW
0010:N/A 0110:N/A 1010:N/A 1110:750
0
Bit 4
PCI/HTTSkw0
RW
0011:N/A 0111:N/A 1011:N/A 1111:900
0
Bit 3
PCISkw3
RW
0000:0
0100:150 1000:300 1100:450
1
Bit 2
PCISkw2
RW
0001:N/A 0101:N/A 1001:N/A 1101:600
1
Bit 1
PCISkw1
RW
0010:N/A 0110:N/A 1010:N/A 1110:750
0
Bit 0
PCISkw0
RW
0011:N/A 0111:N/A 1011:N/A 1111:900
0
I
2
C Table: WD Time Control & Async Frequency Selection Register
Bit 7
ASEL
Async Frequency
Select
RW
0
Bit 6
AEN
AGP/PCI/ Freq Source
Select
RW
1
Bit 5
Reserved
Reserved
RW
X
Bit 4
Reserved
Reserved
RW
X
Bit 3
WDTCtrl
Watch Dog Time base
Control
RW
0
Bit 2
WD2
WD Timer Bit 2
RW
1
Bit 1
WD1
WD Timer Bit 1
RW
1
Bit 0
WD0
WD Timer Bit 0
RW
1
I
2
C Table: VCO Control Select Bit & WD Timer Control Register
Bit 7
M/NEN
M/N Programming
Enable
RW
0
Bit 6
WDEN
Watchdog Enable
RW
0
Bit 5
WDStatus
WD Alarm Status
R
0
Bit 4
WD SF4
RW
0
Bit 3
WD SF3
RW
0
Bit 2
WD SF2
RW
0
Bit 1
WD SF1
RW
0
Bit 0
WD SF0
RW
0
I
2
C Table: VCO Frequency Control Register
Bit 7
N Div8
N Divider Prog bit 8
RW
X
Bit 6
N Div9
N Divider Prog bit 9
RW
X
Bit 5
M Div5
RW
X
Bit 4
M Div4
RW
X
Bit 3
M Div3
RW
X
Bit 2
M Div2
RW
X
Bit 1
M Div1
RW
X
Bit 0
M Div0
RW
X
CPU-PCI/HTT 7 Step
Skew Control (ps)
CPU-PCI 7 Step Skew
Control (ps)
M Divider Programming
bits (5:0)
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table.
VCO Frequency = 14.318 x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
The decimal representation of N Divider in
Byte 11 and 12
Type
0
1
-
-
-
-
-
-
-
-
PWD
Byte 11
Pin #
Name
Control Function
-
Normal
Alarm
-
Watch Dog Safe Freq
Programming bits
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
-
-
-
-
-
Disable
Enable
-
Disable
Enable
1
PWD
Byte 10
Pin #
Name
Control Function
Type
0
-
These bits represent X*290ms (or 1.16S)
the watchdog timer waits before it goes to
alarm mode. Default is 7 X 290ms = 2s.
-
-
-
-
-
-
290ms Base
1160ms Base
-
-
-
66MHz
75.4MHz
FIX PLL
CPU PLL
-
-
Type
0
1
PWD
Byte 9
Pin #
Name
Control Function
-
-
-
-
-
-
-
-
Type
0
1
PWD
Byte 8
Pin #
Name
Control Function
9
ICS950405
0802F--04/22/05
I
2
C Table: VCO Frequency Control Register
Bit 7
N Div7
RW
X
Bit 6
N Div6
RW
X
Bit 5
N Div5
RW
X
Bit 4
N Div4
RW
X
Bit 3
N Div3
RW
X
Bit 2
N Div2
RW
X
Bit 1
N Div1
RW
X
Bit 0
N Div0
RW
X
I
2
C Table: Spread Spectrum Control Register
Bit 7
SSP7
RW
X
Bit 6
SSP6
RW
X
Bit 5
SSP5
RW
X
Bit 4
SSP4
RW
X
Bit 3
SSP3
RW
X
Bit 2
SSP2
RW
X
Bit 1
SSP1
RW
X
Bit 0
SSP0
RW
X
I
2
C Table: Spread Spectrum Control Register
Bit 7
Reserved
Reserved
R
0
Bit 6
SSP14
RW
X
Bit 5
SSP13
RW
X
Bit 4
SSP12
RW
X
Bit 3
SSP11
RW
X
Bit 2
SSP10
RW
X
Bit 1
SSP9
RW
X
Bit 0
SSP8
RW
X
PWD
Byte 12
Pin #
Name
Control Function
-
N Divider Programming
bit (7:0)
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table.
VCO Frequency = 14.318 x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
-
-
-
-
-
-
-
PWD
Byte 13
Pin #
Name
Control Function
PWD
Byte 14
Pin #
Name
Control Function
-
-
0
-
-
Type
0
1
-
Spread Spectrum
Programming b(7:0)
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
-
1
Type
0
1
-
Spread Spectrum
Programming b(14:8)
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
-
-
-
-
-
-
-
-
-
Type
-
-
10
ICS950405
0802F--04/22/05
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+3.8 V
Ambient Operating Temperature . . . . . . . . . . 0C to +70C
Storage Temperature . . . . . . . . . . . . . . . . . . . . 65C to +150C
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+ 0.3
V
Input Low Voltage
V
IL
V
SS
- 0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
5
mA
Input Low Current
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
-5
mA
Input Low Current
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
mA
Operating Supply
Current
I
DD(op)
C
L
= 0 pF; Select @ 100MHz
180
mA
Power Down Supply
Current
I
DDPD
C
L
= 0 pF; With input address to Vdd or
GND
40
mA
Input frequency
F
i
V
DD
= 3.3 V;
11
16
MHz
C
IN
Logic Inputs
5
pF
C
INX
X1 & X2 pins
27
45
pF
Transition Time
1
T
trans
To 1st crossing of target Freq.
3
ms
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target Freq.
3
ms
Skew
1
T
CPU-PCI
V
T
= 1.5 V
1.5
4
ns
1
Guaranteed by design, not 100% tested in production.
Input Capacitance
1
11
ICS950405
0802F--04/22/05
Electrical Characteristics - K8 Push Pull Differential Pair
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
=AMD64 Processor Test Load
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS NOTES
Rising Edge Rate
V/t
2
10
V/ns
1
Falling Edge Rate
V/t
2
10
V/ns
1
Differential Voltage
V
DIFF
0.4
2.3
V
1
Change in V
DIFF_DC
Magnitude
V
DIFF
-150
150
mV
1
Common Mode Voltage
V
CM
1.05
1.45
V
1
Change in Common
Mode Voltage
V
CM
-200
200
mV
1
Jitter, Cycle to cycle
t
jcyc-cyc
Measurement from differential
wavefrom. Maximum difference of cycle
time between 2 adjacent cycles.
0
200
ps
1
Jitter, Accumulated
t
ja
Measured using the JIT2 software
package with a Tek 7404 scope.
TIE (Time Interval Error) measurement
technique:
Sample resolution = 50 ps,
Sample Duration = 10 s
-1000
1000
1,2,3
Duty Cycle
d
t3
Measurement from differential
wavefrom
45
53
%
1
Output Impedance
R
ON
Average value during switching
transition. Used for determining series
termination value.
15
55
1
Group Skew
t
src-skew
Measurement from differential
wavefrom
250
ps
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz
3
Spread Spectrum is off
Measured at the AMD64 processor's
test load. 0 V +/- 400 mV (differential
Measured at the AMD64 processor's
test load. (single-ended measurement)
12
ICS950405
0802F--04/22/05
Electrical Characteristics - ZCLK
T
A
= 0 - 70C; VDD=3.3V +/-5%; C
L
= 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Frequency
F
O1
MHz
Output Impedance
R
DSP1
1
V
O
= V
DD
*(0.5)
12
55
Output High Voltage
V
OH
1
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL
1
I
OL
= 1 mA
0.55
V
Output High Current
I
OH
1
V
OH@MIN
= 1.0 V, V
OH@MAX
= 3.135 V
-33
-33
mA
Output Low Current
I
OL
1
V
OL @MIN
= 1.95 V, V
OL @MAX
= 0.4 V
30
38
mA
Rise Time
t
r1
1
V
OL
= 0.4 V, V
OH
= 2.4 V
0.5
2
ns
Fall Time
t
f1
1
V
OH
= 2.4 V, V
OL
= 0.4 V
0.5
2
ns
Duty Cycle
d
t1
1
V
T
= 1.5 V
45
55
%
Skew t
sk1
1
V
T
= 1.5 V
250
ps
Jitter
t
jcyc-cyc
1
V
T
= 1.5 V 3V66
250
ps
Electrical Characteristics - PCICLK
T
A
= 0 - 70C; V
DD
= 3.3 V,+/-5%; C
L
= 30 pF
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH1
I
OH
= -18 mA
2.1
V
Output Low Voltage
V
OL1
I
OL
= 9.4 mA
0.4
V
Output High Current
I
OH1
V
OH
= 2.0 V
-22
mA
Output Low Current
I
OL1
V
OL
= 0.8 V
16
57
mA
Rise Time
1
t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V
2
ns
Fall Time
1
t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V
2
ns
Duty Cycle
1
d
t1
V
T
= 1.5 V
45
55
%
Skew
1
t
sk1
V
T
= 1.5 V
500
ps
t
jcyc-cyc
1
V
T
= 1.5 V
500
ps
t
jabs1
V
T
= 1.5 V
500
ps
1
Guaranteed by design, not 100% tested in production.
Jitter
13
ICS950405
0802F--04/22/05
Electrical Characteristics - REF
T
A
= 0 - 70C; V
DD
= 3.3 V , +/-5%; C
L
= 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH5
I
OH
= -12 mA
2.6
V
Output Low Voltage
V
OL5
I
OL
= 9 mA
0.4
V
Output High Current
I
OH5
V
OH
= 2.0 V
-22
mA
Output Low Current
I
OL5
V
OL
= 0.8 V
16
mA
Rise Time
1
t
r5
V
OL
= 0.4 V, V
OH
= 2.4 V
4
ns
Fall Time
1
t
f5
V
OH
= 2.4 V, V
OL
= 0.4 V
4
ns
Duty Cycle
1
d
t5
V
T
= 1.5 V
45
55
%
t
jcyc-cyc5
V
T
= 1.5 V
1000
ps
t
jabs5
V
T
= 1.5 V
800
ps
Jitter
1
Electrical Characteristics - AGPCLK
T
A
= 0 - 70C; VDD=3.3V +/-5%; C
L
= 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Frequency
F
O1
MHz
Output Impedance
R
DSP1
1
V
O
= V
DD
*(0.5)
12
55
Output High Voltage
V
OH
1
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL
1
I
OL
= 1 mA
0.55
V
Output High Current
I
OH
1
V
OH@MIN
= 1.0 V, V
OH@MAX
= 3.135 V
-33
-33
mA
Output Low Current
I
OL
1
V
OL @MIN
= 1.95 V, V
OL @MAX
= 0.4 V
30
38
mA
Rise Time
t
r1
1
V
OL
= 0.4 V, V
OH
= 2.4 V
0.5
2
ns
Fall Time
t
f1
1
V
OH
= 2.4 V, V
OL
= 0.4 V
0.5
2
ns
Duty Cycle
d
t1
1
V
T
= 1.5 V
45
55
%
Skew t
sk1
1
V
T
= 1.5 V
250
ps
Jitter
t
jcyc-cyc
1
V
T
= 1.5 V 3V66
250
ps
14
ICS950405
0802F--04/22/05
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS950405
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and
stored into a 5-bit internal data latch. At the end of Power-
On reset, (see AC characteristics for timing values), the
device changes the mode of operations for these pins to
an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
W
8.2K
W
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
15
ICS950405
0802F--04/22/05
Ordering Information
ICS950405yFLF-T
Example:
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
h x 45
h x 45
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
- C -
b
.10 (.004) C
.10 (.004) C
c
L
300 mil SSOP Package
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.03
10.68
.395
.420
E1
7.40
7.60
.291
.299
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
0
8
0
8
MIN
MAX
MIN
MAX
48
15.75
16.00
.620
.630
10-0034
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
SEE VARIATIONS
SEE VARIATIONS
0.635 BASIC
0.025 BASIC
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXX y F LF- T
16
ICS950405
0802F--04/22/05
Revision History
Rev.
Issue Date Description
Page #
0.1
4/21/2005
Updated Byte 11/12 M/N programming description
8-9
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