Integrated
Circuit
Systems, Inc.
ICS950602
0469B--12/18/02
Block Diagram
Pin Configuration
Recommended Application:
VIA Mobile PL133T and PLE133T Chipsets.
Output Features:
2 - CPU clocks @ 2.5V
1 - Pairs of differential CPU clocks @ 3.3V
7 - PCI including 1 free running @ 3.3V
7 - SDRAM @ 3.3V
1 - 48MHz @ 3.3V fixed
1 - 24_48MHz selectable @ 3.3V
2 - REF @ 3.3V, 14.318MHz
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/write
operations.
Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <200ps
CPU Output Skew <175ps
PCI to PCI Output Skew <500ps
Programmable Timing Control HubTM for P
II
/
III
TM
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
48-Pin SSOP & TSSOP
GND
*FS2/REF1
REF0
Vtt_PWRGD#
VDDREF
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X2
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*FS3/PCICLK0
GND
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PCICLK2
PCICLK3
PCICLK4
PCICLK5
SDRAM_IN
*CPU_STOP#
*PCI_STOP#
*PD#
**MULTISEL
GND
SDATA
CPUCLK0
CPUCLK1
VDDCPU_2.5
VDDCPU_3.3
CPUCLKT
CPUCLKC
GND
RESET#
I REF
SDRAM6
GND
SDRAM0
SDRAM1
VDDSDRAM
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDRAM
AVDD48
48MHz/FS0*
24_48MHz/FS1*
SCLK
ICS950602
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
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24
48
47
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45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Host Swing Select Functions
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Integrated
Circuit
Systems, Inc.
ICS950602
0469B--12/18/02
Pin Description
The ICS950602 is a single chip clock solution for VIA Mobile PL133T and PLE133T chipsets. It provides all necessary clock
signals for such a system.
The ICS950602 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With
all these programmable features, ICS' TCH makes motherboard testing, tuning and improvement very simple.
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3
Integrated
Circuit
Systems, Inc.
ICS950602
0469B--12/18/02
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
*See notes on the following page
.
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byt
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byt
e
ACK
ACK
4
Integrated
Circuit
Systems, Inc.
ICS950602
0469B--12/18/02
Byte 0: Functionality and frequency select register (Default=0)
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
t
i
B
n
o
i
t
p
i
r
c
s
e
D
D
W
P
t
i
B
)
4
:
6
,
1
:
2
(
2
t
i
B
1
t
i
B
6
t
i
B
5
t
i
B
4
t
i
B
K
L
C
U
P
C
z
H
M
K
L
C
I
C
P
z
H
M
%
d
a
e
r
p
S
1
e
t
o
N
4
S
F
3
S
F
2
S
F
1
S
F
0
S
F
0
0
0
0
0
0
0
.
0
0
2
0
3
.
3
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
0
0
0
1
0
0
.
0
9
1
0
0
.
8
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
0
0
1
0
0
0
.
0
8
1
0
0
.
6
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
0
0
1
1
0
0
.
0
7
1
0
0
.
4
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
0
1
0
0
0
0
.
6
6
1
0
2
.
3
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
0
1
0
1
0
0
.
0
6
1
0
0
.
2
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
0
1
1
0
0
0
.
0
5
1
0
5
.
7
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
0
1
1
1
0
0
.
5
4
1
0
3
.
6
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
1
0
0
0
0
0
.
0
4
1
0
0
.
5
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
1
0
0
1
0
0
.
6
3
1
0
0
.
4
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
1
0
1
0
0
0
.
0
3
1
0
5
.
2
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
1
0
1
1
0
0
.
4
2
1
0
0
.
1
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
1
1
0
0
0
2
.
7
6
0
6
.
3
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
1
1
0
1
0
9
.
0
0
1
3
6
.
3
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
1
1
1
0
0
0
.
8
1
1
0
3
.
9
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
0
1
1
1
1
0
4
.
4
3
1
0
6
.
3
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
0
0
0
0
0
0
.
7
6
0
5
.
3
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
0
0
0
1
0
5
.
0
0
1
0
5
.
3
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
0
0
1
0
0
0
.
5
1
1
0
3
.
8
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
0
0
1
1
0
9
.
3
3
1
7
4
.
3
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
0
1
0
0
0
8
.
6
6
0
4
.
3
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
0
1
0
1
0
2
.
0
0
1
0
4
.
3
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
0
1
1
0
0
0
.
0
1
1
0
7
.
6
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
0
1
1
1
0
6
.
3
3
1
0
4
.
3
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
1
0
0
0
0
0
.
5
0
1
0
0
.
5
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
1
0
0
1
0
0
.
0
9
0
0
.
0
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
1
0
1
0
0
0
.
5
8
0
3
.
8
2
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
1
0
1
1
0
0
.
8
7
0
0
.
9
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
1
1
0
0
0
6
.
6
6
0
3
.
3
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
1
1
0
1
0
0
.
0
0
1
0
3
.
3
3
d
a
e
r
p
s
n
w
o
d
%
5
.
0
-
o
t
0
1
1
1
1
0
0
0
.
5
7
0
5
.
7
3
d
a
e
r
p
s
r
e
t
n
e
c
%
5
2
.
0
-
/
+
1
1
1
1
1
0
3
.
3
3
1
0
3
.
3
3
d
a
e
r
p
s
n
w
o
d
%
5
.
0
-
o
t
0
3
t
i
B
s
t
u
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n
i
d
e
h
c
t
a
l
,
t
c
e
l
e
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r
a
w
d
r
a
h
y
b
d
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t
c
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s
s
i
y
c
n
e
u
q
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r
F
-
0
4
:
7
,
2
t
i
B
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
1
0
0
t
i
B
l
a
m
r
o
N
-
0
e
l
b
a
n
e
m
u
r
t
c
e
p
s
d
a
e
r
p
S
-
1
0
7
t
i
B
s
t
u
p
n
i
h
c
t
a
l
y
b
d
e
t
c
e
l
e
s
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b
ll
i
w
y
c
n
e
u
q
e
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e
f
a
s
g
o
d
h
c
t
a
W
-
0
)
0
:
4
(
t
i
b
0
1
e
t
y
B
y
b
d
e
m
m
a
r
g
o
r
p
e
b
ll
i
w
y
c
n
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u
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f
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f
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s
g
o
d
h
c
t
a
W
-
1
0
5
Integrated
Circuit
Systems, Inc.
ICS950602
0469B--12/18/02
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Byte 4: Output Control Register
(1 = enable, 0 = disable)
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
-
X
k
c
a
b
d
a
e
R
4
S
F
6
t
i
B
-
X
k
c
a
b
d
a
e
R
3
S
F
5
t
i
B
-
X
k
c
a
b
d
a
e
R
2
S
F
4
t
i
B
-
X
k
c
a
b
d
a
e
R
1
S
F
3
t
i
B
-
X
k
c
a
b
d
a
e
R
0
S
F
2
t
i
B
8
4
1
0
K
L
C
U
P
C
1
t
i
B
7
4
1
1
K
L
C
U
P
C
0
t
i
B
3
4
,
4
4
1
C
K
L
C
U
P
C
,
T
K
L
C
U
P
C
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
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c
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e
D
7
t
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B
9
3
1
6
M
A
R
D
S
6
t
i
B
0
1
1
F
_
K
L
C
I
C
P
5
t
i
B
7
1
1
5
K
L
C
I
C
P
4
t
i
B
6
1
1
4
K
L
C
I
C
P
3
t
i
B
5
1
1
3
K
L
C
I
C
P
2
t
i
B
4
1
1
2
K
L
C
I
C
P
1
t
i
B
3
1
1
1
K
L
C
I
C
P
0
t
i
B
1
1
1
0
K
L
C
I
C
P
t
i
B
#
n
i
P
D
W
P
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p
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c
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D
7
t
i
B
-
0
e
l
b
a
s
i
D
=
0
,
e
l
b
a
n
E
=
1
t
c
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t
e
d
t
f
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h
s
r
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e
g
T
E
S
E
R
6
t
i
B
-
0
8
4
=
1
,
4
2
=
0
:
8
4
_
4
2
L
E
S
5
t
i
B
7
2
1
z
H
M
8
4
4
t
i
B
6
2
1
z
H
M
8
4
_
4
2
3
t
i
B
-
0
d
e
v
r
e
s
e
R
2
t
i
B
0
3
,
1
3
1
)
5
:
4
(
M
A
R
D
S
1
t
i
B
3
3
,
4
3
1
)
3
:
2
(
M
A
R
D
S
0
t
i
B
6
3
,
7
3
1
)
1
:
0
(
M
A
R
D
S
t
i
B
#
n
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P
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P
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7
t
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-
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c
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L
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T
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6
t
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B
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d
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R
5
t
i
B
-
X
d
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v
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R
4
t
i
B
-
X
d
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R
3
t
i
B
-
X
d
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v
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2
t
i
B
-
X
d
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R
1
t
i
B
-
X
d
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0
t
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B
-
X
d
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