Integrated
Circuit
Systems, Inc.
ICS950703
0690D--05/14/04
Recommended Application:
Intel Tehema and Tehema-E Chipsets
Output Features:
4 Differential CPU Clock Pairs @ 3.3V
2 - 3V MREF clocks for memory reference seeds,
(separate single ended but 180 degrees out of phase)
4 - 66MHz 3V66 output
10 - 3V 33MHz PCI clocks
2 - 48MHz clocks (180 degrees out of phase)
2 - 14.318 reference output (180 degrees out of phase)
Key Specifications:
3V66 Output jitter <300ps
CPU Output Jitter <200ps
MREF Output jitter <250ps
Programmable Timing Control Hub
TM
for P4
TM
Features/Benefits:
QuadRom
TM
frequency selection.
Programmable asynchronous 3V66/PCI frequency.
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/write
operations.
Uses external 14.318MHz reference input.
Frequency Table
Bit4
Bit3
Bit2
Bit1
Bit0
CPU
MREF
PCI
3V66
Sel133/100
FS3
FS2
FS1
FS0
MHz
MHz
MHz
MHz
0
0
0
0
0
90.00
45.00
30.00
60.00
0
0
0
0
1
100.00
50.00
33.33
66.67
0
0
0
1
0
100.90
50.45
33.63
67.27
0
0
0
1
1
103.00
51.50
34.33
68.67
0
0
1
0
0
105.00
52.50
35.00
70.00
0
0
1
0
1
108.00
54.00
36.00
72.00
0
0
1
1
0
110.00
55.00
36.67
73.33
0
0
1
1
1
112.00
56.00
37.33
74.67
0
1
0
0
0
115.00
57.50
38.33
76.67
0
1
0
0
1
118.00
59.00
39.33
78.67
0
1
0
1
0
120.00
60.00
40.00
80.00
0
1
0
1
1
122.00
61.00
40.67
81.33
0
1
1
0
0
125.00
62.50
41.67
83.33
0
1
1
0
1
127.00
63.50
42.33
84.67
0
1
1
1
0
130.00
65.00
43.33
86.67
0
1
1
1
1
133.60
66.80
44.53
89.07
1
0
0
0
0
120.00
60.00
30.00
60.00
1
0
0
0
1
133.33
66.67
33.33
66.67
1
0
0
1
0
133.90
66.95
33.48
66.95
1
0
0
1
1
136.00
68.00
34.00
68.00
1
0
1
0
0
138.00
69.00
34.50
69.00
1
0
1
0
1
140.00
70.00
35.00
70.00
1
0
1
1
0
142.00
71.00
35.50
71.00
1
0
1
1
1
144.00
72.00
36.00
72.00
1
1
0
0
0
145.00
72.50
36.25
72.50
1
1
0
0
1
148.00
74.00
37.00
74.00
1
1
0
1
0
150.00
75.00
37.50
75.00
1
1
0
1
1
152.00
76.00
38.00
76.00
1
1
1
0
0
154.00
77.00
38.50
77.00
1
1
1
0
1
156.00
78.00
39.00
78.00
1
1
1
1
0
158.00
79.00
39.50
79.00
1
1
1
1
1
160.00
80.00
40.00
80.00
GND 1
56 VDDMREF
MULTSEL0/REF0 2
55 3VMREF
MULTSEL1/REF1 3
54 3VMREF_B
VDDREF
4
53 GNDMREF
X1 5
52 SCLK
X2 6
51 CPUCLKT3
GNDREF
7
50 CPUCLKC3
PCICLK0 8
49 VDDCPU
PCICLK1 9
48 CPUCLKT2
VDDPCI 10
47 CPUCLKC2
PCICLK2 11
46 GNDCPU
PCICLK3 12
45 CPUCLKT1
GNDPCI 13
44 CPUCLKC1
PCICLK4 14
43 VDDCPU
PCICLK5 15
42 CPUCLKT0
VDDPCI 16
41 CPUCLKC0
PCICLK6 17
40 GNDCPU
**FS2/PCICLK7 18
39 IREF
GNDPCI 19
38 AVDD
**FS3/PCICLK8 20
37 GND
**SEL100_133#/PCICLK9 21
36 VDD3V66
VDDPCI 22
35 3V66_3
SDATA 23
34 3V66_2
GND48 24
33 GND3V66
*FS0/48MHz_0 25
32 GND3V66
**FS1/48MHz_1 26
31 3V66_1
AVDD48 27
30 3V66_0
PD# 28
29 VDD3V66
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
Pin Configuration
56-SSOP
I
C
S
9
50
703
2
Integrated
Circuit
Systems, Inc.
ICS950703
0690D--05/14/04
Power Groups
The ICS950703 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with Rambus RDRAM
memory. It provides all necessary clock signals for such a system.
The ICS950703 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially
programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios,
selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/
N control can configure output frequency with resolution up to 0.1MHz increment. This part also provides 128 frequency selections
via ICS QuadROM
TM
technology as an alternate to M/N programming.
General Description
Block Diagram
PLL2
Frequency
Dividers
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
X1
X2
XTAL
MULTSEL (1:0)
FS (3:0)
SDATA
SCLK
PD#
SEL100_133#
Control
Logic
48MHZ (1:0)
REF (1:0)
PCICLK (9 :0)
3V66 (3:0)
MREF_B
MREF
I REF
4
4
CPUCLKT (3:0)
CPUCLKC (3:0)
AVDD
GND
4
7
REF output, Crystal
27
24
48MHz fixed, Fixed PLL
38
37
CPU PLL, CPU Master Clock,
VDD
GND
--
10, 16, 22
13, 19
PCI outputs
29, 36
32, 33
3V66 outputs
43, 49
40, 46
CPU Outputs, IREF, MULTSEL
56
53
MREF outputs
Pin Number
Description
Integrated
Circuit
Systems, Inc.
ICS950703
0690D--05/14/04
Pin Description
3
PIN
PIN
PIN
#
NAME
TYPE
1
GND
PWR Ground pin.
2
MULTSEL0/REF0
I/O
3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference
clock.
3
MULTSEL1/REF1
I/O
3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference
clock.
4
VDDREF
PWR Ref, XTAL power supply, nominal 3.3V
5
X1
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
6
X2
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
7
GNDREF
PWR Ground pin for the REF outputs.
8
PCICLK0
OUT PCI clock output.
9
PCICLK1
I/O
Watchdog enable latch input/ 3.3V PCI clock output.
10
VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
11
PCICLK2
OUT PCI clock output.
12
PCICLK3
OUT PCI clock output.
13
GNDPCI
PWR Ground pin for the PCI outputs
14
PCICLK4
OUT PCI clock output.
15
PCICLK5
OUT PCI clock output.
16
VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
17
PCICLK6
OUT PCI clock output.
18
**FS2/PCICLK7
I/O
Frequency select latch input pin / 3.3V PCI clock output.
19
GNDPCI
PWR Ground pin for the PCI outputs
20
**FS3/PCICLK8
I/O
Frequency select latch input pin / 3.3V PCI clock output.
21
**SEL100_133#/PCICLK9
I/O
Latched select input for 100 or 133.3MHz selection. 0=133MHz, 1 = 100MHz / 3.3V PCI
clock output.
22
VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
23
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
24
GND48
PWR Ground pin for the 48MHz outputs
25
*FS0/48MHz_0
I/O
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
26
**FS1/48MHz_1
I/O
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
27
AVDD48
PWR Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V
28
PD#
IN
Asynchronous active low input pin, with 120Kohm internal pull-up resistor, used to power
down the device. The internal clocks are disabled and the VCO and the crystal are stopped.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 2X drive
DESCRIPTION
4
Integrated
Circuit
Systems, Inc.
ICS950703
0690D--05/14/04
Pin Description (Continued)
PIN
PIN
PIN
#
NAME
TYPE
29
VDD3V66
PWR Power pin for the 3V66 clocks.
30
3V66_0
OUT 3.3V 66.66MHz clock output
31
3V66_1
OUT 3.3V 66.66MHz clock output
32
GND3V66
PWR Ground pin for the AGP outputs
33
GND3V66
PWR Ground pin for the AGP outputs
34
3V66_2
OUT 3.3V 66.66MHz clock output
35
3V66_3
OUT 3.3V 66.66MHz clock output
36
VDD3V66
PWR Power pin for the 3V66 clocks.
37
GND
PWR Ground pin.
38
AVDD
PWR 3.3V Analog Power pin for Core PLL
39
IREF
OUT
This pin establishes the reference current for the differential current-mode output pairs. This
pin requires a fixed precision resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
40
GNDCPU
PWR Ground pin for the CPU outputs
41
CPUCLKC0
OUT
Complimentary clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
42
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
43
VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
44
CPUCLKC1
OUT
Complimentary clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
45
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
46
GNDCPU
PWR Ground pin for the CPU outputs
47
CPUCLKC2
OUT
Complimentary clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
48
CPUCLKT2
OUT
True clock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
49
VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
50
CPUCLKC3
OUT
Complimentary clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
51
CPUCLKT3
OUT
True clock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
52
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
53
GNDMREF
PWR Ground pin for the 3VMREF outputs.
54
3VMREF_B
OUT 3V reference output to memory clock driver (180 degree out of phase with 3VMREF)
55
3VMREF
OUT 3V reference output to memory clock driver
56
VDDMREF
PWR Power supply for 3VMREF clocks, nominal 3.3V
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 2X drive
DESCRIPTION
5
Integrated
Circuit
Systems, Inc.
ICS950703
0690D--05/14/04
Maximum Allowed Current
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Pin Description
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