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ICS951104
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Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Block Diagram
0485E--04/26/02
Pin Configuration
Recommended Application:
ALI 1671/1672 P4 Chipset
Output Features:
2 - Pairs of differential CPU clocks (differential current mode)
2 - AGP @ 3.3V
7 - PCI @ 3.3V
1 - 48MHz @ 3.3V fixed
1 - REF @ 3.3V, 14.318MHz
7 - Pairs of differential SSTL2 DDR @ 2.5V
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/write operations.
Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <150ps
AGP Output Jitter <250ps
DDR Output Jitter <250ps
CPU - DDR Skew <250ps
CPU - AGP/PCI Skew = 2.5ns 500ps
Programmable Timing Control Hub
TM
for P4
TM
56-Pin 300-mil SSOP, 240-mil TSSOP
AVDD_CORE
X1
X2
GND
VDD
MULT_SEL/REF0
RESET#
VDD
FS0/AGP0
AGP1
GND
FS1/PCICLK_E
FS2/PCICLK0
PCICLK1
PCICLK2
GND
VDD
PCICLK3
PCICLK4
PCICLK5
PCI_STOP#
Vtt_PWRGD/PD#
AVDD48
FS3/48MHz
GND
SDATA
SCLK
CLK_STOP#
*
**
*
*
*
**
1
*
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
IREF
GNDIREF
GNDCPU
DDRT0
GND
VDDL
VDDL
GND
GND
VDDL
DDRC0
DDRT1
DDRC1
DDRT2
DDRC2
DDRT3
DDRC3
DDRT4
DDRC4
DDRT5
DDRC5
DDRT6
DDRC6
ICS951104
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PLL2
PLL1
Spread
Spectrum
48MHz
REF0
PCICLK (5:0)
AGP (1:0)
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
AGP
DIVDER
DDR
DIVDER
PD#
MULTSEL
SDATA
SCLK
Vtt_PWRGD
CLK_STOP#
PCI_STOP#
FS (3:0)
I REF
RESET#
Control
Logic
Config.
Reg.
2
7
7
2
2
7
CPUCLKT (1:0)
DDRC (6:0)
CPUCLKC (1:0)
DDRT (6:0)
PCICLK_E
Stop
Stop
Stop
Stop
Functionality
Host Swing Select Functions
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to GND
FS3
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FS0
CPU
DDR
AG P
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1
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PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
change without notice.
background image
2
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
The ICS951104 is a single chip clock solution for desktop designs using the ALI 1671/1672 P4 Chipset. It provides all
necessary clock signals for such a system.
The ICS951104 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
General Description
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0
:
1
(
T
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U
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C
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U
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e
5
5
,
2
5
)
0
:
1
(
C
K
L
C
U
P
C
T
U
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s
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u
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Pin Description
o
background image
3
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
*See notes on the following page
.
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byt
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byt
e
ACK
ACK
background image
4
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The I
2
C readback of the power up default indicates the revision ID in bits 2, 7:4 as shown.
t
i
B
n
o
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t
p
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e
D
D
W
P
,
2
t
i
B
4
:
7
t
i
B
3
S
F
2
S
F
1
S
F
0
S
F
K
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C
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P
C
)
z
H
M
(
R
D
D
)
z
H
M
(
P
G
A
)
z
H
M
(
K
L
C
I
C
P
)
z
H
M
(
e
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P
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S
0
0
0
0
0
1
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t
o
N
2
t
i
B
7
t
i
B
6
t
i
B
5
t
i
B
4
t
i
B
0
0
0
0
0
6
6
.
6
6
6
6
.
6
6
6
6
.
6
6
3
3
.
3
3
d
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t
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C
%
5
2
.
0
-
/
+
0
0
0
0
1
6
6
.
6
6
0
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
d
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S
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C
%
5
2
.
0
-
/
+
0
0
0
1
0
0
0
.
0
0
1
6
6
.
6
6
6
6
.
6
6
3
3
.
3
3
d
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C
%
5
2
.
0
-
/
+
0
0
0
1
1
0
0
.
0
0
1
0
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
d
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S
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C
%
5
2
.
0
-
/
+
0
0
1
0
0
0
0
.
0
0
1
3
3
.
3
3
1
6
6
.
6
6
3
3
.
3
3
d
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C
%
5
2
.
0
-
/
+
0
0
1
0
1
3
3
.
3
3
1
6
6
.
6
6
6
6
.
6
6
3
3
.
3
3
d
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S
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C
%
5
2
.
0
-
/
+
0
0
1
1
0
3
3
.
3
3
1
0
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
d
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S
r
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C
%
5
2
.
0
-
/
+
0
0
1
1
1
3
3
.
3
3
1
3
3
.
3
3
1
6
6
.
6
6
3
3
.
3
3
d
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p
S
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t
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C
%
5
2
.
0
-
/
+
0
1
0
0
0
6
6
.
6
6
6
6
.
6
6
6
6
.
6
6
3
3
.
3
3
d
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D
%
5
.
0
-
o
t
0
0
1
0
0
1
6
6
.
6
6
0
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
d
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r
p
S
n
w
o
D
%
5
.
0
-
o
t
0
0
1
0
1
0
0
0
.
0
0
1
6
6
.
6
6
6
6
.
6
6
3
3
.
3
3
d
a
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r
p
S
n
w
o
D
%
5
.
0
-
o
t
0
0
1
0
1
1
0
0
.
0
0
1
0
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
d
a
e
r
p
S
n
w
o
D
%
5
.
0
-
o
t
0
0
1
1
0
0
0
0
.
0
0
1
3
3
.
3
3
1
6
6
.
6
6
3
3
.
3
3
d
a
e
r
p
S
n
w
o
D
%
5
.
0
-
o
t
0
0
1
1
0
1
3
3
.
3
3
1
6
6
.
6
6
6
6
.
6
6
3
3
.
3
3
d
a
e
r
p
S
n
w
o
D
%
5
.
0
-
o
t
0
0
1
1
1
0
3
3
.
3
3
1
0
0
.
0
0
1
6
6
.
6
6
3
3
.
3
3
d
a
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r
p
S
n
w
o
D
%
5
.
0
-
o
t
0
0
1
1
1
1
3
3
.
3
3
1
3
3
.
3
3
1
6
6
.
6
6
3
3
.
3
3
d
a
e
r
p
S
n
w
o
D
%
5
.
0
-
o
t
0
1
0
0
0
0
0
0
.
0
7
0
0
.
0
7
0
0
.
0
7
0
0
.
5
3
d
a
e
r
p
S
r
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t
n
e
C
%
5
2
.
0
-
/
+
1
0
0
0
1
0
0
.
0
0
1
7
6
.
6
6
1
0
5
.
2
6
5
2
.
1
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
0
1
0
0
0
.
5
0
1
0
0
.
0
7
0
0
.
0
7
0
0
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
0
1
1
0
0
.
5
0
1
0
0
.
5
0
1
0
0
.
0
7
0
0
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
1
0
0
0
0
.
5
0
1
0
0
.
0
4
1
0
0
.
0
7
0
0
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
1
0
1
0
0
.
0
0
1
7
6
.
6
6
1
3
4
.
1
7
2
7
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
1
1
0
0
0
.
0
4
1
0
0
.
5
0
1
0
0
.
0
7
0
0
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
1
1
1
0
0
.
0
4
1
0
0
.
0
4
1
0
0
.
0
7
0
0
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
0
0
0
0
3
.
3
3
1
0
6
.
6
6
1
3
3
.
3
3
5
6
.
6
6
f
f
O
d
a
e
r
p
S
1
1
0
0
1
3
3
.
3
7
0
0
.
0
1
1
3
3
.
3
7
6
6
.
6
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
0
1
0
0
0
.
0
1
1
3
3
.
3
7
3
3
.
3
7
6
6
.
6
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
0
1
1
0
0
.
0
1
1
0
0
.
0
1
1
3
3
.
3
7
6
6
.
6
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
1
0
0
0
0
.
0
1
1
6
6
.
6
4
1
3
3
.
3
7
6
6
.
6
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
1
0
1
6
6
.
6
4
1
3
3
.
3
7
3
3
.
3
7
6
6
.
6
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
1
1
0
6
6
.
6
4
1
0
0
.
0
1
1
3
3
.
3
7
6
6
.
6
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
1
1
1
6
6
.
6
4
1
6
6
.
6
4
1
3
3
.
3
7
6
6
.
6
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
3
t
i
B
s
t
u
p
n
I
d
e
h
c
t
a
L
,
t
c
e
l
e
s
e
r
a
w
d
r
a
h
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
0
4
:
7
,
2
t
i
B
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
1
0
1
t
i
B
l
a
m
r
o
N
-
0
d
e
l
b
a
n
E
m
u
r
t
c
e
p
S
d
a
e
r
p
S
-
1
0
0
t
i
B
g
n
i
n
n
u
R
-
0
s
t
u
p
t
u
o
ll
a
e
t
a
t
s
i
r
T
-
1
0
background image
5
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Byte 4: Output Control Register
(1 = enable, 0 = disable)
ti
B
#
n
i
P
D
W
P
n
o
it
p
i
r
c
s
e
D
7
ti
B
4
2
1
Z
H
M
8
4
6
ti
B
7
4
,
8
4
1
0
C
/
T
R
D
D
5
ti
B
-
1
e
l
b
a
s
i
D
=
0
,
e
l
b
a
n
E
=
1
t
c
e
t
e
d
tf
i
h
s
r
a
e
g
t
e
s
e
R
4
ti
B
,
1
4
,
2
4
3
4
,
4
4
1
)
1
:
2
(
C
/
T
R
D
D
3
ti
B
,
5
3
,
6
3
7
3
,
8
3
1
)
3
:
4
(
C
/
T
R
D
D
2
ti
B
,
9
2
,
0
3
1
3
,
2
3
1
)
5
:
6
(
C
/
T
R
D
D
1
ti
B
0
1
1
1
P
G
A
0
ti
B
9
1
0
P
G
A
ti
B
#
n
i
P
D
W
P
n
o
it
p
i
r
c
s
e
D
7
ti
B
2
1
1
E
_
K
L
C
I
C
P
6
ti
B
0
2
1
5
_
K
L
C
I
C
P
5
ti
B
4
ti
B
9
1
1
4
_
K
L
C
I
C
P
3
ti
B
8
1
1
3
_
K
L
C
I
C
P
2
ti
B
5
1
1
2
_
K
L
C
I
C
P
1
ti
B
4
1
1
1
_
K
L
C
I
C
P
0
ti
B
3
1
1
0
_
K
L
C
I
C
P
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
-
0
e
l
b
a
p
p
o
t
S
=
1
;
n
u
R
e
e
r
F
=
0
,
ti
b
e
l
b
a
n
e
P
O
T
S
_
K
L
C
a
i
v
p
o
t
S
0
C
/
T
U
P
C
6
ti
B
-
0
e
l
b
a
p
p
o
t
S
=
1
;
n
u
R
e
e
r
F
=
0
,
ti
b
e
l
b
a
n
e
P
O
T
S
_
K
L
C
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1
C
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5
ti
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l
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4
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,
ti
b
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3
ti
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=
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n
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ti
b
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)
0
:
6
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C
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2
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ti
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0
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1
ti
B
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w
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h
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#
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#
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7
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5
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1
3
ti
B
-
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k
c
a
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d
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R
3
S
F
2
ti
B
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k
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1
ti
B
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k
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1
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0
ti
B
-
X
k
c
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R
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F