Integrated
Circuit
Systems, Inc.
ICS951702
Advance Information
0664--07/29/02
Block Diagram
Functionality
Pin Configuration
56-Pin 240 mil TSSOP
Recommended Application:
1644 and 1644T applications using DDR
Output Features:
7 - Differential pairs DDR SDRAM clocks
3 - CPU @ 2.5V (1 - Free running)
8 - PCI @ 3.3V (1 - Free running and 1 - 2 X optional)
2 - AGP @ 3.3V
1 - IOAPIC @ 2.5V
1 - 48MHz, @3.3V
1 - REF @ 3.3V
Features:
Up to 147MHz frequency support
Power management through PD#
Spread spectrum for EMI control (0 to -0.5% down
spread, 0.25% center spread).
Uses external 14.318MHz crystal
Skew Specifications:
CPU - CPU: <250ps
PCI - PCI: <500ps
SDRAM - SDRAM: <250ps
AGP - AGP: <250ps
PCI - AGP: <750ps
CPU - SDRAM: <750ps
CPU - PCI: <3ns
P
III
TM System Clock Chip for DDR SDRAM
Notes:
* Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down of 120K to GND
1. PCICLK6 is selectable 2X via I
2
C
Note:
PCICLK = 33.33MHz
AGP = 66.66MHz
FS3
FS2
FS1
FS0
CPU
SDRAM
0
0
0
0
66.66
66.66
0
0
0
1
66.66
100.00
0
0
1
0
100.00
66.66
0
0
1
1
100.00
100.00
0
1
0
0
100.00
133.33
0
1
0
1
133.33
66.66
0
1
1
0
133.33
100.00
0
1
1
1
133.33
133.33
1
0
0
0
66.66
66.66
1
0
0
1
66.66
100.00
1
0
1
0
100.00
66.66
1
0
1
1
100.00
100.00
1
1
0
0
100.00
133.33
1
1
0
1
133.33
66.66
1
1
1
0
133.33
100.00
1
1
1
1
133.33
133.33
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
VDDL
IOAPIC
GND
X1
X2
AVDD
FS0/REF
VDD
PCICLK0
PCICLK1
PCICLK2
GND
VDD
**
**FS1/AGP0
AGP1
GND
**FS2/PCI_F
PCICLK3
PCICLK4
PCICLK5
GND
VDD
PCICLK6
*PCI_STOP#
*CPU_STOP#
*Vtt_PWRGD/PD#
VDD
**FS3/48MHz
1
VDDL
CPUCLK_F
CPUCLK0
CPUCLK1
GND
DDRT0
DDRC0
GND
VDDL
SCLK
SDATA
GND
DDRT1
DDRC1
DDRT2
DDRC2
VDDL
GND
DDRT3
DDRC3
DDRT4
DDRC4
GND
VDDL
DDRT5
DDRC5
DDRT6
DDRC6
ICS951702
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Vtt_PWRGD/PD#
MODE
SDATA
SCLK
FS (3:0)
PLL2
PLL1
Spread
Spectrum
48MHz
CPUCLK (1:0)
IOAPIC
AGP (1:0)
2
2
X1
X2
XTAL
OSC
CPU
DIVDER
AGP
DIVDER
REF0
Control
Logic
Config.
Reg.
SDRAM
DIVDER
DDRC (6:0)
DDRT (6:0)
7
7
PCICLK (6:0)
5
PCICLK_F
PCI
DIVDER
Stop
Stop
CPUCLK_F
2
ICS951702
Advance Information
0664--07/29/02
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Internal pull-down resistor of 120K to GND on indicated inputs.
3:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 36, 43, 48, 56
VDDL
PWR
Power supply pins, nominal 2.5V
2
IOAPIC
OUT
2.5V clock outputs
3, 11, 16, 21,
29, 37, 42, 49,
52
GND
PWR
Ground pins
4
X1
IN
Crystal input,nominally 14.318MHz.
5
X2
OUT
Crystal output, nominally 14.318MHz.
6
AVDD
PWR
Analog power supply for 3.3V
FS0
2, 3
IN
Frequency select pin.
REF0
OUT
14.318 MHz reference clock.
8, 17, 22, 27
VDD
PWR
Power supply pins, nominal 3.3V
FS1
2, 3
IN
Frequency select pin.
AGP0
OUT
AGP outputs defined as 2X PCI.
10
AGP1
OUT
AGP output defined as 2X PCI.
PCICLK_F
OUT
Free running PCI clock
FS2
1, 2
IN
Frequency select pin.
20, 19, 18, 15,
14, 13
PCICLK (5:0)
OUT
PCI clock outputs.
23
PCICLK6
OUT
PCI clock output (selectable 1X or 2X via I
2
C)
24
PCI_STOP#
IN
Stops all PCICLKs at logic 0 level, when input low besides the
PCICLK_F clocks which are controllable by I
2
C bits whether they are
free running or stopped by PCI_STOP.
25
CPU_STOP#
IN
Stops all CPUCLKs at logic 0 level, when input low. The individual
CPU clocks are controllable by I
2
C bits whether they are free
running or stopped by CPU_STOP.
PD#
IN
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms.
Vtt_PWRGD
IN
This pin acts as a dual function input pin for Vtt_PWRGD and PD#
signal. When Vtt_PWRGD goes high the frequency select will be
latched at power on thereafter the pin is an asynchronous active low
power down pin.
FS3
2, 3
IN
Frequency select pin
48MHz
OUT
48MHz output clock
30
SDATA
I/O
Data pin for I
2
C circuitry 5V tolerant
31
SCLK
IN
Clock pin of I
2
C circuitry 5V tolerant
33, 35, 39, 41,
45, 47, 51
DDRT (6:0)
OUT
"True" clocks of differential pair DDR SDRAM outputs - 2.5V
32, 34, 38, 40,
44, 46, 50
DDRC (6:0)
OUT
"Complementry" clocks of differential pair
DDR SDRAM outputs - 2.5V
53, 54
CPUCLK (1:0)
OUT
2.5V CPU clocks
55
CPUCLK_F
OUT
Free running CPU clock. Not affected by the CPU_STOP#.
9
7
12
28
26
3
ICS951702
Advance Information
0664--07/29/02
General Description
The ICS951702 is a main clock synthesizer chip for PIII based systems with ALI 1644 style chipset. This provides all
clocks required for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS951702
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
Power Groups
AVDD = PLL Core & Xtal
VDD48 = 48MHz, PLL2
VDDL, VDD = Digital
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ICS951702
Advance Information
0664--07/29/02
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The I
2
C readback of the power up default indicates the revision ID in bits 2, 7:4 as shown.
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7
,
2
t
i
B
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
1
0
1
t
i
B
l
a
m
r
o
N
-
0
d
e
l
b
a
n
E
m
u
r
t
c
e
p
S
d
a
e
r
p
S
-
1
0
0
t
i
B
g
n
i
n
n
u
R
-
0
s
t
u
p
t
u
o
ll
a
e
t
a
t
s
i
r
T
-
1
0
5
ICS951702
Advance Information
0664--07/29/02
Byte 1: Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
#
3
S
F
6
t
i
B
0
1
1
1
P
G
A
5
t
i
B
9
1
0
P
G
A
4
t
i
B
8
2
1
z
H
M
8
4
3
t
i
B
2
1
C
I
P
A
O
I
2
t
i
B
5
5
1
F
_
K
L
C
U
P
C
1
t
i
B
4
5
1
0
K
L
C
U
P
C
0
t
i
B
3
5
1
1
K
L
C
U
P
C
Byte 2: Active/Inactive Register
(1= enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Byte 4: Active/Inactive Register
(1= enable, 0 = disable)
Byte 5: Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Active/Inactive Register
(1= enable, 0 = disable)
Note: Don't write into this register, writing into this
register can cause malfunction
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
d
e
v
r
e
s
e
R
6
t
i
B
-
0
d
e
v
r
e
s
e
R
5
t
i
B
-
0
d
e
v
r
e
s
e
R
4
t
i
B
-
0
d
e
v
r
e
s
e
R
3
t
i
B
-
0
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
3
1
1
0
K
L
C
I
C
P
6
t
i
B
4
1
1
1
K
L
C
I
C
P
5
t
i
B
5
1
1
2
K
L
C
I
C
P
4
t
i
B
8
1
1
3
K
L
C
I
C
P
3
t
i
B
9
1
1
4
K
L
C
I
C
P
2
t
i
B
0
5
,
1
5
1
0
C
M
A
R
D
S
,
0
T
M
A
R
D
S
1
t
i
B
6
4
,
7
4
1
1
C
M
A
R
D
S
,
1
T
M
A
R
D
S
0
t
i
B
4
4
,
5
4
1
2
C
M
A
R
D
S
,
2
T
M
A
R
D
S
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
#
0
S
F
6
t
i
B
-
X
#
1
S
F
5
t
i
B
-
X
#
2
S
F
4
t
i
B
2
1
1
F
_
K
L
C
I
C
P
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
8
3
,
9
3
1
3
C
M
A
R
D
S
,
3
T
M
A
R
D
S
1
t
i
B
4
3
,
5
3
1
4
C
M
A
R
D
S
,
4
T
M
A
R
D
S
0
t
i
B
2
3
,
3
3
1
5
C
M
A
R
D
S
,
5
T
M
A
R
D
S
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
0
2
1
5
K
L
C
I
C
P
5
t
i
B
3
2
1
6
K
L
C
I
C
P
4
t
i
B
3
2
1
X
2
=
0
,
X
1
=
1
;
6
K
L
C
I
C
P
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
,
3
3
2
3
1
6
C
M
A
R
D
S
,
6
T
M
A
R
D
S
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