Integrated
Circuit
Systems, Inc.
ICS952301
Advance Information
0673--07/09/02
Block Diagram
Frequency Timing Generator for Transmeta Systems
Pin Configuration
Pentium is a trademark on Intel Corporation.
Power Groups
VDD_Core, GND_Core = PLL core
VDDREF, GNDREF = REF, X1, X2
VDDPCI, GNDPCI = PCICLK (6:0)
VDD48, GND48 = 48MHz (1:0)
28-Pin 173mil TSSOP
Note: ^ Internal Pulldown Resistor
* Internal Pullup Resistor
1 1X/2X Programmable
Recommended Application:
Transmeta
Output Features:
1CPU up to 66.6MHz &
overclocking of 66MHz.
7 PCI (3.3V) @ 33.3MHz (all are free running
selectable) w/ 2 selectable 1X/2X.
1 REF (3.3V) at 14.318MHz.
1 48MHz (3.3V).
1 24_48MHz selectable output.
Features:
Supports Spread Spectrum modulation for CPU and
PCI clocks, default -2.0% downspread.
Efficient Power management scheme through stop
clocks and power down modes.
Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
28-pin TSSOP package, 4.40mm (173mil).
Skew Characteristics:
PCI PCI < 500ps
CPU(early) PCI = 1.5ns 4ns.
GNDREF 1
28 VDDREF
X1 2
27 REF/ 1X or 2X Programmable
*
X2 3
26 CPU_STOP#
PD# 4
25 VDDCPU/CORE
PCICLK0 5
24 GNDCPU/CORE
PCICLK1 6
23 CPUCLK0
GNDPCI 7
22 PCI_STOP#
VDDPCI 8
21 SCLK
PCICLK2
1
9
20 VDD48
PCICLK3 10
19 GND48
PCICLK4
1
11
18 48MHz
GNDPCI 12
17 24-48MHz/Sel 48_24#
*
VDDPCI 13
16 SDATA
PCICLK5 14
15 PCICLK6
952301A
G
SEL48_24#
XTAL
OSC
CPU
PLL
48MHz
PLL
Control
Logic
X1
X2
SDATA
SCLOCK
PD#
48MHz
REF
STOP
STOP
24/48
STOP
STOP
CPU_STOP#
24/48MHz
PCI_STOP#
CPU
PCI(6:0)
PCI DIV
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
2
ICS952301
Advance Information
0673--07/09/02
Pin Descriptions
PIN # PIN
PIN
TYPE
DESCRIPTION
1
GNDREF
PWR
Ground pin.
2
X1
IN
Crystal input, nominally 14.318MHz.
3
X2
OUT
Crystal output, nominally 14.318MHz.
4
PD#
IN
Asynchronous active low input pin used to power down the
device into a low power state. The internal clocks are
disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
5
PCICLK0
OUT
PCI clock outputs.
6
PCICLK1
OUT
PCI clock outputs.
7
GNDPCI
PWR
Ground pin.
8
VDDPCI
PWR
Supply for PCI, nominal 3.3V.
9
PCICLK21
OUT
PCI clock outputs.
10
PCICLK3
OUT
PCI clock outputs.
11
PCICLK41
OUT
PCI clock outputs.
12
GNDPCI
PWR
Ground pin.
13
VDDPCI
PWR
Supply for PCI, nominal 3.3V.
14
PCICLK5
OUT
PCI clock outputs.
15
PCICLK6
OUT
PCI clock outputs.
16
SDATA
I/O
Data pin for I
2
C circuitry 5V tolerant
17
24-48MHz/Sel
48_24#*
I/O
Selectable 48 or 24MHz output
18
48MHz
OUT
48MHz output clock
19
GND48
PWR
Ground pin.
20
VDD48
PWR
Power for 24 & 48MHz output buffers and fixed PLL core.
21
SCLK
IN
Clock pin of I
2
C circuitry 5V tolerant
22
PCI_STOP#
IN
Stops all PCICLKs besides the PCICLK_F clocks at logic 0
level, when input low
23
CPUCLK0
OUT
CPU clock outputs.
24
GNDCPU/CORE
PWR
Ground pin.
25
VDDCPU/CORE
PWR
3.3V power for the PLL core.
26
CPU_STOP#
IN
Stops all CPUCLKs besides the CPUCLK_F clocks at logic 0
level, when input low
27
REF/ 1X or 2X
Programmable*
OUT
14.318 MHz reference clock. Latched input select for strength
of PCICLK(4,2). Default 1X with internal pullup.
28
VDDREF
PWR
3.3V power for the REF.
3
ICS952301
Advance Information
0673--07/09/02
ICS952301 Power Management Requirements
CPU
PCI
Byte 0
PCICLK
PCICLK
24
48
REF
PD#
STOP#
STOP#
Bit 0
CPUCLK
0
Not Free
Run
Free-Run
MHz
MHZ
0
X
X
X
STOP
LOW
LOW
LOW
LOW
LOW
LOW
1
0
1
0
RUN
STOP
RUN
RUN
RUN
RUN
RUN
1
1
0
0
RUN
RUN
STOP
RUN
RUN
RUN
RUN
1
1
1
1
RUN
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Note: If Byte 3 bit [7:2]=0 Not Free-Run, can be controlled by PCI_STOP#
If Byte 3 bit [7:2]=1 Free-Run, cannot controlled by PCI_STOP#
VCO
4
ICS952301
Advance Information
0673--07/09/02
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 6
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Read:
5
ICS952301
Advance Information
0673--07/09/02
Note: PWD = Power-Up Default
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Bit2
Bit7
Bit6
Bit5
Bit4
FS4
FS3
FS2
FS1
FS0
0
0
0
0
0
60
30
0
0
0
0
1
60
30
0
0
0
1
0
60
30
0
0
0
1
1
60
30
0
0
1
0
0
66.6
33.3
0
0
1
0
1
66.6
33.3
0
0
1
1
0
66.6
33.3
0
0
1
1
1
66.6
33.3
0
1
0
0
0
67.32
33.66
0
1
0
0
1
68.64
34.32
0
1
0
1
0
69.96
34.98
0
1
0
1
1
72.6
36.3
0
1
1
0
0
61.5
30.75
0
1
1
0
1
63
31.5
0
1
1
1
0
64
32
0
1
1
1
1
65
32.5
Bit
1
0
0
0
0
60
30
2,7:4
1
0
0
0
1
66.6
33.3
1
0
0
1
0
50
25
1
0
0
1
1
48
24
1
0
1
0
0
58.8
29.4
1
0
1
0
1
57.6
28.8
1
0
1
1
0
56.4
28.2
1
0
1
1
1
54
27
1
1
0
0
0
60
30
1
1
0
0
1
60
30
1
1
0
1
0
60
30
1
1
0
1
1
60
30
1
1
1
0
0
66.6
33.3
1
1
1
0
1
66.6
33.3
1
1
1
1
0
66.6
33.3
1
1
1
1
1
66.6
33.3
Bit3
Bit1
0-Normal 1-Spread spectrun Enabled
Bit0
0-Running 1-Tristate all outputs
Reserved
Bit
CPU
PCI
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