Integrated
Circuit
Systems, Inc.
ICS952302
0957B--10/05/04
Frequency Generator for Transmeta
TM
Efficeon
TM
Pin Configuration
Recommended Application:
Transmeta Efficion, ATi M6
Output Features:
3 - CPUs @ 3.3V including 1 free running
CPUCLK_F
7 - PCI @ 3.3V, including 4 free running PCICLK_F
1 - 27MHz clock @ 3.3V
2 - 48MHz clocks @ 3.3V
2 - REF clocks @3.3V
Key Specifications:
CPU output jitter: < 250ps
PCI output skew: < 250ps
CPUT - PCI output skew: 1-3ns
27MHz Accuracy < 50ppm
48MHz Accuracy < 50ppm
Functionality
Features:
Support I2C Index read/write and block read/write
operations.
Uses external 14.318MHz referience input or XTAL.
Full Load Power consumption reduced >10%
compared to reference device
Power management via SMBus
0
0
0
+/-0.3
0
0
1
+/-0.6
0
1
0
+/-0.25
0
1
1
+/-0.45
1
0
0
-0.60%
1
0
1
-1.20%
1
1
0
-0.50%
1
1
1
-0.90%
DOWN
Spread
%
Byte 4b7
Byte 4b6
Byte 4b5
CENTER
VDDREF
1
48
REF1
REF0
2
47
VDDCPU
GNDREF
3
46
N/C
X1
4
45
CPUCLK0
X2
5
44
GNDCPU
VDDPCI
6
43
CPUCLK1
PCICLK_F0
7
42
CPUCLK_F
PCICLK_F1
8
41
CPU_STOP#
GNDPCI
9
40
GND
PCICLK0
10
39
N/C
PCICLK1
11
38
OE*
PCICLK_F2
12
37
N/C
PCICLK_F3
13
36
VDD
VDDPCI
14
35
N/C
PCICLK2
15
34
VDD27
GNDPCI
16
33
GND
N/C
17
32
27MHZ
N/C
18
31
N/C
VDDCOR
19
30
N/C
PCI_STOP#
20
29
N/C
**PD#
21
28
GND48
GND48
22
27
VDD48
SDATA
23
26
48MHZ_1
SCLK
24
25
48MHZ_0
48-TSSOP
* Internal Pull-Up Resistor
**No Diode Clamp to VDD
IC
S95
2302
2
ICS952302
0957B--10/05/04
Pin Descriptions
PIN #
PIN NAME
PIN
TYPE
DESCRIPTION
1
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
2
REF0
OUT
14.318 MHz reference clock.
3
GNDREF
PWR
Ground pin for the REF outputs.
4
X1
IN
Crystal input, Nominally 14.318MHz.
5
X2
OUT
Crystal output, Nominally 14.318MHz
6
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
7
PCICLK_F0
OUT
Free running PCI clock not affected by PCI_STOP# .
8
PCICLK_F1
OUT
Free running PCI clock not affected by PCI_STOP# .
9
GNDPCI
PWR
Ground pin for the PCI outputs
10
PCICLK0
OUT
PCI clock output.
11
PCICLK1
OUT
PCI clock output.
12
PCICLK_F2
OUT
Free running PCI clock not affected by PCI_STOP# .
13
PCICLK_F3
OUT
Free running PCI clock not affected by PCI_STOP# .
14
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
15
PCICLK2
OUT
PCI clock output.
16
GNDPCI
PWR
Ground pin for the PCI outputs
17
N/C
N/C
No Connection.
18
N/C
N/C
No Connection.
19
VDDCOR
PWR
3.3V power for the PLL core.
20
PCI_STOP#
IN
Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input.
21
**PD#
IN
Asynchronous active low input pin, with 120Kohm internal pull-up resistor, used to power down the device. The
internal clocks are disabled and the VCO and the crystal are stopped.
22
GND48
PWR
Ground pin for the 48MHz outputs
23
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
24
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
25
48MHZ_0
OUT
48MHz clock output.
26
48MHZ_1
OUT
48MHz clock output.
27
VDD48
PWR
Power pin for the 48MHz output.3.3V
28
GND48
PWR
Ground pin for the 48MHz outputs
29
N/C
N/C
No Connection.
30
N/C
N/C
No Connection.
31
N/C
N/C
No Connection.
32
27MHZ
OUT
27.0000MHz Video Clock for ATi Chipset
33
GND
PWR
Ground pin.
34
VDD27
PWR
Power pin for the 27MHz output.3.3V
35
N/C
N/C
No Connection.
36
VDD
PWR
Power supply, nominal 3.3V
37
N/C
N/C
No Connection.
38
OE*
IN
Active high input for enabling Memory Channel outputs.
0 = tri-state outputs, 1= enable outputs
39
N/C
N/C
No Connection.
40
GND
PWR
Ground pin.
41
CPU_STOP#
IN
Stops all CPUCLK, except those set to be free running clocks
42
CPUCLK_F
OUT
Free running CPU clock. Not affected by the CPU_STOP#.
43
CPUCLK1
OUT
CPU clock outputs. 3.3V
44
GNDCPU
PWR
Ground pin for the CPU outputs
45
CPUCLK0
OUT
CPU clock outputs. 3.3V
46
N/C
N/C
No Connection.
47
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
48
REF1
OUT
14.318 MHz reference clock.
* Internal Pull-Up Resistor
** No diode clamp to VDD.
3
ICS952302
0957B--10/05/04
Spread spectrum may be enabled through SMBus programming. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The
ICS952302 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process
and temperature variations.
General Description
Block Diagram
(1:0)
(1:0)
27MHz
(1:0)
(2:0)
(3:0)
1
1
PD#
OE
4
4
ICS952302
0957B--10/05/04
Control
Function
Bit 7
CPUCLK_F
Output Enable
RW
Disable
Enable
1
Bit 6
CPUCLK0
Output Enable
RW
Disable
Enable
1
Bit 5
CPUCLK1
Output Enable
RW
Disable
Enable
1
Bit 4
27MHZ
Output Enable
RW
Disable
Enable
1
Bit 3
48MHZ_0
Output Enable
RW
Disable
Enable
1
Bit 2
48MHZ_1
Output Enable
RW
Disable
Enable
1
Bit 1
REF0
Output Enable
RW
Disable
Enable
1
Bit 0
REF1
Output Enable
RW
Disable
Enable
1
Control
Function
Bit 7
PCICLK_F0
Test Mode
RW
Disable
Enable
1
Bit 6
PCICLK_F1
Output Enable
RW
Disable
Enable
1
Bit 5
PCICLK_F2
Output Enable
RW
Disable
Enable
1
Bit 4
PCICLK_F3
Output Enable
RW
Disable
Enable
1
Bit 3
PCICLK0
Spread Control
RW
Disable
Enable
1
Bit 2
PCICLK1
Output Enable
RW
Disable
Enable
1
Bit 1
PCICLK2
Output Enable
RW
Disable
Enable
1
Bit 0
Spread Spectrum
Mode
Spread Control for PLL1
RW
OFF
ON
0
Control
Function
Bit 7
CPUCLK_F
RW
Free Running
Stoppable
0
Bit 6
CPUCLK0
RW
Free Running
Stoppable
1
Bit 5
CPUCLK1
RW
Free Running
Stoppable
1
Bit 4
Reserved
Reserved
RW
-
-
x
Bit 3
Reserved
Reserved
RW
-
-
x
Bit 2
CPU_STOP
Stop all CPU clocks
RW
Enable
Disable
1
Bit 1
Reserved
Reserved
RW
-
-
x
Bit 0
CPU_STOP#
PCI_STOP#
H/w or S/w Select
RW
H/W
I2C
1
Control
Function
Bit 7
PCICLK_F0
RW
Free Running
Stoppable
0
Bit 6
PCICLK_F1
RW
Free Running
Stoppable
0
Bit 5
PCICLK_F2
RW
Free Running
Stoppable
0
Bit 4
PCICLK_F3
RW
Free Running
Stoppable
0
Bit 3
PCICLK0
RW
Free Running
Stoppable
1
Bit 2
PCICLK1
RW
Free Running
Stoppable
1
Bit 1
PCICLK2
RW
Free Running
Stoppable
1
Bit 0
PCI_STOP
Stop all PCI clocks
RW
Enable
Disable
1
7
8
11
12
15
-
13
10
PWD
0
1
Byte 1
Pin #
Name
Type
2
48
43
32
25
26
PWD
45
Byte 0
Pin #
Name
Type
42
0
1
Note: Byte2bit2=0 (Enable) to stop all CPUCLK's ONLY when Byte2 bit(5:7) at STOPPABLE MODE
Pin #
Name
Type
11
Allow assertion of
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop PCI
clocks
45
Allow assertion of
CPU_STOP# or setting of
CPU_STOP control bit in
SMBus register to stop
CPU clocks
20, 41
7
15
-
13
43
(note)
-
-
-
12
8
Byte 3
10
SMBus Table: Output Control Register
1
0
PWD
SMBus Table: Output Control Register
SMBus Table: Output Control Register
SMBus Table: Output Control Register
0
Byte 2
Pin #
Name
Type
PWD
1
42
5
ICS952302
0957B--10/05/04
Control
Function
Bit 7
Spread Position
Center or Down SS
RW
Center
Down
1
Bit 6
SS1
Spread Bit 1
RW
0
Bit 5
SS2
Spread Bit 2
RW
0
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Control
Function
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Control
Function
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
SMBus Table: Vendor & Revision ID Register
Control
Function
Bit 7
RID3
R
-
-
x
Bit 6
RID2
R
-
-
x
Bit 5
RID1
R
-
-
x
Bit 4
RID0
R
-
-
x
Bit 3
VID3
R
-
-
0
Bit 2
VID2
R
-
-
0
Bit 1
VID1
R
-
-
0
Bit 0
VID0
R
-
-
1
See SS Table
1
Reserved
Reserved
Reserved
SMBus Table: Control Register
Reserved
Reserved
Reserved
Reserved
Pin #
-
Name
Name
1
SMBus Table: Control Register
0
-
-
-
-
PWD
Reserved
-
-
-
-
-
-
-
-
-
-
-
Byte 4
Pin #
-
PWD
-
-
-
-
Byte 6
Pin #
-
-
SMBus Table: Spread Spectrum Control Register
Type
PWD
Type
Reserved
Reserved
-
-
VENDOR ID
-
-
Byte 7
Pin #
Reserved
Reserved
Reserved
PWD
-
REVISION ID
-
-
-
0
Reserved
Reserved
-
0
Byte 5
Reserved
Reserved
Reserved
1
Type
Name
Reserved
Reserved
Reserved
Name
Type
0
1
6
ICS952302
0957B--10/05/04
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . 0C to +70C
Case Temperature . . . . . . . . . . . . . . . . . . . . . 115C
Storage Temperature . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+ 0.3
V
Input Low Voltage
V
IL
V
SS
- 0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
5
mA
Input Low Current
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
-5
mA
Input Low Current
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
mA
Operating Supply Current
I
DD(op)
C
L
= (full load); 66MHz
102
150
mA
Power Down Supply
Current
I
DDPD
C
L
= 0 pF; With input address to Vdd or GND
320
600
A
Input frequency
F
i
V
DD
= 3.3 V;
11
14.3132
16
MHz
C
IN
Logic Inputs
5
pF
C
INX
X1 & X2 pins
27
45
pF
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target Freq.
3
5.5
ms
Skew
1
T
CPU-PCI
V
T
= 1.5 V
1
1.5
4
ns
1
Guaranteed by design, not 100% tested in production.
Input Capacitance
1
7
ICS952302
0957B--10/05/04
Electrical Characteristics - CPU
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH2B
I
OH
= -20 mA
2.4
2.9
V
Output Low Voltage
V
OL2B
I
OL
= 12 mA
0.25
0.4
V
V
OUT
= 1 V
-67
-29
V
OUT
= 3.135V
-23
-8
V
OUT
= 1.95 V
27
56
V
OUT
=0.4V
23
30
Rise Time
1
t
r2B
V
OL
= 0.4 V, V
OH
= 2.4 V
1
1.4
2
ns
Fall Time
1
t
f2B
V
OH
= 2.4 V, V
OL
= 0.4 V
1
1.4
2
ns
Duty Cycle
1
d
t2B
V
T
= 1.5 V
45
51.5
55
%
Skew
1
t
sk2B
V
T
= 1.5 V
60
175
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
V
T
= 1.5 V
175
250
ps
1
Guaranteed by design, not 100% tested in production.
Output High Current
I
OH2B
mA
Output Low Current
I
OL2B
mA
Electrical Characteristics - PCICLK, PCICLK_F
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH2B
I
OH
= -20 mA
2.4
2.9
V
Output Low Voltage
V
OL2B
I
OL
= 12 mA
0.25
0.4
V
V
OUT
= 1 V
-67
-29
V
OUT
= 3.135V
-23
-8
V
OUT
= 1.95 V
27
56
V
OUT
=0.4V
23
30
Rise Time
1
t
r2B
V
OL
= 0.4 V, V
OH
= 2.4 V
1
1.3
2
ns
Fall Time
1
t
f2B
V
OH
= 2.4 V, V
OL
= 0.4 V
1
1.2
2
ns
Duty Cycle
1
d
t2B
V
T
= 1.5 V
45
50.5
55
%
Skew
1
t
sk2B
V
T
= 1.5 V
68
250
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
V
T
= 1.5 V
100
250
ps
1
Guaranteed by design, not 100% tested in production.
Output Low Current
I
OL2B
mA
Output High Current
I
OH2B
mA
8
ICS952302
0957B--10/05/04
Electrical Characteristics - 27MHz
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Frequency Accuracy
F
ACC
REF Out = 14.31818MHz
-50
0
50
ppm
Output High Voltage
V
OH2B
I
OH
= -20 mA
2.4
2.9
V
Output Low Voltage
V
OL2B
I
OL
= 12 mA
0.25
0.4
V
V
OUT
= 1 V
-67
-29
V
OUT
= 3.135V
-23
-8
V
OUT
= 1.95 V
27
56
V
OUT
=0.4V
23
30
Rise Time
1
t
r2B
V
OL
= 0.4 V, V
OH
= 2.4 V
1
1.1
2
ns
Fall Time
1
t
f2B
V
OH
= 2.4 V, V
OL
= 0.4 V
1
1.2
2
ns
Duty Cycle
1
d
t2B
V
T
= 1.5 V
45
51
55
%
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
V
T
= 1.5 V
340
400
ps
1
Guaranteed by design, not 100% tested in production.
Output High Current
I
OH2B
mA
Output Low Current
I
OL2B
mA
Electrical Characteristics - 48MHz
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Frequency Accuracy
F
ACC
REF Out = 14.31818MHz
-50
0
50
ppm
Output High Voltage
V
OH2B
I
OH
= -20 mA
2.4
2.9
V
Output Low Voltage
V
OL2B
I
OL
= 12 mA
0.25
0.4
V
V
OUT
= 1 V
-67
-29
V
OUT
= 3.135V
-23
-8
V
OUT
= 1.95 V
27
56
V
OUT
=0.4V
23
30
Rise Time
1
t
r2B
V
OL
= 0.4 V, V
OH
= 2.4 V
1
1.1
2
ns
Fall Time
1
t
f2B
V
OH
= 2.4 V, V
OL
= 0.4 V
1
1.5
2
ns
Duty Cycle
1
d
t2B
V
T
= 1.5 V
45
52
55
%
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
V
T
= 1.5 V
200
350
ps
1
Guaranteed by design, not 100% tested in production.
mA
mA
Output High Current
I
OH2B
Output Low Current
I
OL2B
9
ICS952302
0957B--10/05/04
Electrical Characteristics - REF
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Frequency Accuracy
F
ACC
REF Out = 14.31818MHz
-50
0
50
ppm
Output High Voltage
V
OH2B
I
OH
= -20 mA
2.4
2.9
V
Output Low Voltage
V
OL2B
I
OL
= 12 mA
0.25
0.4
V
V
OUT
= 1 V
-67
-29
V
OUT
= 3.135V
-23
-8
V
OUT
= 1.95 V
27
56
V
OUT
=0.4V
23
30
Rise Time
1
t
r2B
V
OL
= 0.4 V, V
OH
= 2.4 V
1
1.3
2
ns
Fall Time
1
t
f2B
V
OH
= 2.4 V, V
OL
= 0.4 V
1
1.7
2
ns
Duty Cycle
1
d
t2B
V
T
= 1.5 V
45
53
55
%
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
V
T
= 1.5 V
270
500
ps
1
Guaranteed by design, not 100% tested in production.
Output High Current
I
OH2B
mA
Output Low Current
I
OL2B
mA
10
ICS952302
0957B--10/05/04
General SMBus serial interface information for the ICS952302
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1 (see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byt
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byt
e
ACK
ACK
11
ICS952302
0957B--10/05/04
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up,
they act as input pins. The logic level (voltage) that is
present on these pins at this time is read and stored into
a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an
output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
W
8.2K
W
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
12
ICS952302
0957B--10/05/04
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 4 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PCI_STOP# and CLK_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping
and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS952302 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
CPUCLK
PCICLK
VCO
Crystal
PD#
13
ICS952302
0957B--10/05/04
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CLK_STOP# is synchronized by the ICS952302. The minimum that the CPU clock is enabled (CLK_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS952302.
3. CLK_STOP# signal.
4. All other clocks continue to run undisturbed.
PCICLK
CPUCLK _F
PCI_STOP# (High)
CLK_STOP#
INTERNAL
CPUCLK
14
ICS952302
0957B--10/05/04
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS952302. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS952302 internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is
one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS952302 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS952302.
3. All other clocks continue to run undisturbed.
4. CLK_STOP# is shown in a high (true) state.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CLK_STOP#
PCICLK
PCI_STOP#
15
ICS952302
0957B--10/05/04
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
- C -
- C -
b
c
L
aaa
C
Ordering Information
ICS952302yGLF-T
6.10 mm. Body, 0.50 mm. pitch TSSOP
(240 mil)
(0.020 mil)
MIN
MAX
MIN
MAX
A
--
1.20
--
.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
D
E
E1
6.00
6.20
.236
.244
e
L
0.45
0.75
.018
.030
N
0
8
0
8
aaa
--
0.10
--
.004
VARIATIONS
MIN
MAX
MIN
MAX
48
12.40
12.60
.488
.496
10-0039
N
D mm.
D (inch)
Reference Doc.: JEDEC Publication 95, M O-153
0.50 BASIC
0.020 BASIC
SEE VARIATIONS
SEE VARIATIONS
SEE VARIATIONS
SEE VARIATIONS
8.10 BASIC
0.319 BASIC
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
Example:
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXX y G LF- T
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