Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
0875--05/24/04
Pin Configuration
Recommended Application:
CK410 compliant clock
Output Features:
2 - 0.7V current-mode differential CPU pairs
1 - 0.7V current-mode differential SRC pair
6 - PCI (33MHz)
3 - PCICLK_F, (33MHz) free-running
1 - USB, 48MHz
1 - 24/48 MHz
1 - DOT, 96MHz, 0.7V current differential pair
2 - REF, 14.318MHz
5 - PCI-Express 0.7V current differential pairs
Key Specifications:
CPU/SRC outputs cycle-cycle jitter < 85ps
PCI outputs cycle-cycle jitter < 250ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
Programmable Timing Control HubTM for Next Gen P
4
TM processor
Functionality
Features/Benefits:
Programmable output frequencies
Programmable output skew.
Programmable spread percentage for EMI control.
Programmable watch dog safe frequency.
Supports tight ppm accuracy clocks for Serial-ATA
Supports spread spectrum modulation, 0 to -0.5%
down spread, 0.25% center spread, and 0.3%
center spread
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Supports undriven differential CPU, SRC pair in PD#
for power management.
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
GND 1
56 VDDPCI
PCICLK3 2
55 PCICLK2
PCICLK4 3
54 PCICLK1
PCICLK5 4
53 PCICLK0
GND 5
52 Reset#
VDDPCI 6
51 REF0/FS
L
C
PCICLK_F0 7
50 REF1
FS
L
A/PCICLK_F1 8
49 GND
FS
L
B/PCICLK_F2 9
48 X1
VDD48 10
47 X2
**SEL24_48#/24_48MHz 11
46 VDDREF
USB_48MHz 12
45 SCLK
GND 13
44 SDATA
DOTT_ 96MHz 14
43 CPUCLKT0
DOTC_96MHz 15
42 CPUCLKC0
Vtt_PwrGd#/PD 16
41 VDDCPU
PCIEXT0 17
40 CPUCLKT1
PCIEXC0 18
39 CPUCLKC1
VDDPCIEX 19
38 GND
GND 20
37 IREF
PCIEXT1 21
36 GNDA
PCIEXC1 22
35 VDDA
PCIEXT2 23
34 VDDPCIEX
PCIEXC2 24
33 PCIEXT4
GND 25
32 PCIEXC4
SRCCLKT 26
31 PCIEXT3
SRCCLKC 27
30 PCIEXC3
VDDSRC 28
29 GND
I
C
S
9541
19
56-Pin SSOP
** Internal Pull-Down Resistor
* Internal Pull-Up Resistor
Bit2
Bit1
Bit0
CPU
PCIEX
SRC
PCI
FSLC FSLB FSLA
MHz
MHz
MHz
MHz
0
0
0
0
0
266.66
100.00
100.00
33.33
0
0
0
0
1
133.33
100.00
100.00
33.33
0
0
0
1
0
200.00
100.00
100.00
33.33
0
0
0
1
1
166.66
100.00
100.00
33.33
0
0
1
0
0
333.33
100.00
100.00
33.33
0
0
1
0
1
100.00
100.00
100.00
33.33
0
0
1
1
0
400.00
100.00
100.00
33.33
0
0
1
1
1
200.00
100.00
100.00
33.33
0
1
0
0
0
266.66
133.33
133.33
33.33
0
1
0
0
1
133.33
133.33
133.33
33.33
0
1
0
1
0
200.00
133.33
133.33
33.33
0
1
0
1
1
166.66
125.00
125.00
33.33
0
1
1
0
0
333.33
125.00
125.00
33.33
0
1
1
0
1
100.00
133.33
133.33
33.33
0
1
1
1
0
400.00
133.33
133.33
33.33
0
1
1
1
1
200.00
133.33
133.33
33.33
1
0
0
0
0
269.33
101.00
101.00
33.67
1
0
0
0
1
134.66
101.00
101.00
33.67
1
0
0
1
0
202.00
101.00
101.00
33.67
1
0
0
1
1
168.33
101.00
101.00
33.67
1
0
1
0
0
274.66
103.00
103.00
34.33
1
0
1
0
1
137.33
103.00
103.00
34.33
1
0
1
1
0
206.00
103.00
103.00
34.33
1
0
1
1
1
171.66
103.00
103.00
34.33
1
1
0
0
0
279.99
105.00
105.00
35.00
1
1
0
0
1
140.00
105.00
105.00
35.00
1
1
0
1
0
210.00
105.00
105.00
35.00
1
1
0
1
1
174.99
105.00
105.00
35.00
1
1
1
0
0
287.99
108.00
108.00
36.00
1
1
1
0
1
144.00
108.00
108.00
36.00
1
1
1
1
0
216.00
108.00
108.00
36.00
1
1
1
1
1
179.99
108.00
108.00
36.00
* Entries 00111 & 01111 are 250MHz on the B & C revision.
Bit4
Bit3
2
Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
0875--05/24/04
Pin Description
PIN # PIN NAME
PIN
TYPE
DESCRIPTION
1
GND
PWR
Ground pin.
2
PCICLK3
OUT
PCI clock output.
3
PCICLK4
OUT
PCI clock output.
4
PCICLK5
OUT
PCI clock output.
5
GND
PWR
Ground pin.
6
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
7
PCICLK_F0
OUT
Free running PCI clock not affected by PCI_STOP# .
8
FSLA/PCICLK_F1
I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 3.3V PCI free running clock
output.
9
FSLB/PCICLK_F2
I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values./ 3.3V PCI free running clock
output.
10
VDD48
PWR
Power pin for the 48MHz output.3.3V
11
**SEL24_48#/24_48MHz
I/O
Latched select input for 24/48MHz output / 24/48MHz clock output.
1=24MHz, 0 = 48MHz.
12
USB_48MHz
OUT
48.00MHz USB clock
13
GND
PWR
Ground pin.
14
DOTT_ 96MHz
OUT
True clock of differential pair for 96.00MHz DOT clock.
15
DOTC_96MHz
OUT
Complement clock of differential pair for 96.00MHz DOT clock.
16
Vtt_PwrGd#/PD
IN
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin
used to put the device into a low power state. The internal clocks, PLLs
and the crystal oscillator are stopped.
17
PCIEXT0
OUT
True clock of differential PCI_Express pair.
18
PCIEXC0
OUT
Complement clock of differential PCI_Express pair.
19
VDDPCIEX
PWR
Power supply for PCI Express clocks, nominal 3.3V
20
GND
PWR
Ground pin.
21
PCIEXT1
OUT
True clock of differential PCI_Express pair.
22
PCIEXC1
OUT
Complement clock of differential PCI_Express pair.
23
PCIEXT2
OUT
True clock of differential PCI_Express pair.
24
PCIEXC2
OUT
Complement clock of differential PCI_Express pair.
25
GND
PWR
Ground pin.
26
SRCCLKT
OUT
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
27
SRCCLKC
OUT
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
28
VDDSRC
PWR
Supply for SRC clocks, 3.3V nominal
3
Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
0875--05/24/04
Pin Description
PIN # PIN NAME
TYPE
DESCRIPTION
29
GND
PWR
Ground pin.
30
PCIEXC3
OUT
Complement clock of differential PCI_Express pair.
31
PCIEXT3
OUT
True clock of differential PCI_Express pair.
32
PCIEXC4
OUT
Complement clock of differential PCI_Express pair.
33
PCIEXT4
OUT
True clock of differential PCI_Express pair.
34
VDDPCIEX
PWR
Power supply for PCI Express clocks, nominal 3.3V
35
VDDA
PWR
3.3V power for the PLL core.
36
GNDA
PWR
Ground pin for the PLL core.
37
IREF
OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
38
GND
PWR
Ground pin.
39
CPUCLKC1
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
40
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
41
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
42
CPUCLKC0
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
43
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
44
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
45
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
46
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
47
X2
OUT
Crystal output, Nominally 14.318MHz
48
X1
IN
Crystal input, Nominally 14.318MHz.
49
GND
PWR
Ground pin.
50
REF1
OUT
14.318 MHz reference clock.
51
REF0/FSLC
I/O
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values.
52
Reset#
OUT
Real time system reset signal for frequency gear ratio change or watchdog
timer timeout. This signal is active low.
53
PCICLK0
OUT
PCI clock output.
54
PCICLK1
OUT
PCI clock output.
55
PCICLK2
OUT
PCI clock output.
56
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
4
Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
0875--05/24/04
ICS954119 follows Intel CK410 Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS954119 is driven with a 14.318MHz crystal.
General Description
Block Diagram
I REF
PLL2
Frequency
Dividers
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
48MHz, USB
X1
X2
XTAL
SDATA
SCLK
Vtt_PWRGD#/PD
FSLA
FSLB
FSLC
Sel24/48
Control
Logic
REF (1:0)
CPUCLKT (1:0)
CPUCLKC (1:0)
SRCCLKT
SRCCLKC
PCICLK (5:0)
PCICLKF (2:0)
PCI-Express (4:0)
Reset#
DOTT_96MHz
DOTC_96MHz
24/48MHz
Power Busing
VDD
6,56
10
19,34
28
35
41
46
GND
Description
1,5
PCI pads and Prepad
13
USB _48M Hz, DOT_96M Hz, Fix P LL
20,29
Differnetial PCIEX pair
25
Differnetial SRC pair
36
Analog Core, CPU PLL
38
Differnetial CPU pair
49
Xtal, Ref, CPU PLL Digital
5
Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
0875--05/24/04
General I
2
C serial interface information for the ICS954119
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byt
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byt
e
ACK
ACK
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