Integrated
Circuit
Systems, Inc.

ICS9DB108

0723D--01/08/04

Pin Configuration

Recommended Application:

DB800 Intel Yellow Cover part with PCI-Express support.

Output Features:

8 - 0.7V current-mode differential output pairs

Supports zero delay buffer mode and fanout mode

Bandwidth programming available

Key Specifications:

Outputs cycle-cycle jitter < 50ps

Outputs skew: 50ps

+/- 300ppm frequency accuracy on output clocks

Features/Benefits:

Supports tight ppm accuracy clocks for Serial-ATA

Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread

Supports undriven differential output pair in PD# and
SRC_STOP# for power management.

Eight Output Differential Buffer for PCI-Express

48-pin SSOP & TSSOP

SRC_DIV#

48 VDDA

VDD

47 GNDA

GND

46 IREF

SRC_IN

45 LOCK

SRC_IN#

44 OE_7

OE_0

43 OE_4

OE_3

42 DIF_7

DIF_0

41 DIF_7#

DIF_0#

40 GND

GND 10

39 VDD

VDD 11

38 DIF_6

DIF_1 12

37 DIF_6#

DIF_1# 13

36 OE_6

OE_1 14

35 OE_5

OE_2 15

34 DIF_5

DIF_2 16

33 DIF_5#

DIF_2# 17

32 GND

GND 18

31 VDD

VDD 19

30 DIF_4

DIF_3 20

29 DIF_4#

DIF_3# 21

28 HIGH_BW#

BYPASS#/PLL 22

27 SRC_STOP#

SCLK 23

26 PD#

SDATA 24

25 GND

ICS9DB108

Integrated
Circuit
Systems, Inc.

ICS9DB108

0723D--01/08/04

Pin Description

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

SRC_DIV#

Active low Input for determining SRC output frequency SRC or
SRC/2.
0 = SRC/2, 1= SRC

VDD

PWR

Power supply, nominal 3.3V

GND

PWR

Ground pin.

SRC_IN

0.7 V Differential SRC TRUE input

SRC_IN#

0.7 V Differential SRC COMPLEMENTARY input

OE_0

Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs

OE_3

Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs

DIF_0

OUT

0.7V differential true clock outputs

DIF_0#

OUT

0.7V differential complement clock outputs

GND

PWR

Ground pin.

VDD

PWR

Power supply, nominal 3.3V

DIF_1

OUT

0.7V differential true clock outputs

DIF_1#

OUT

0.7V differential complement clock outputs

OE_1

Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs

OE_2

Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs

DIF_2

OUT

0.7V differential true clock outputs

DIF_2#

OUT

0.7V differential complement clock outputs

GND

PWR

Ground pin.

VDD

PWR

Power supply, nominal 3.3V

DIF_3

OUT

0.7V differential true clock outputs

DIF_3#

OUT

0.7V differential complement clock outputs

BYPASS#/PLL

Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode

SCLK

Clock pin of SMBus circuitry, 5V tolerant.

SDATA

I/O

Data pin for SMBus circuitry, 5V tolerant.

Integrated
Circuit
Systems, Inc.

ICS9DB108

0723D--01/08/04

Pin Description (Continued)

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

GND

PWR

Ground pin.

PD#

Asynchronous active low input pin used to power down the
device. The internal clocks are disabled and the VCO and the
crystal are stopped.

SRC_STOP#

Active low input to stop diff outputs.

HIGH_BW#

PWR

3.3V input for selecting PLL Band Width
0 = High, 1= Low

DIF_4#

OUT

0.7V differential complement clock outputs

DIF_4

OUT

0.7V differential true clock outputs

VDD

PWR

Power supply, nominal 3.3V

GND

PWR

Ground pin.

DIF_5#

OUT

0.7V differential complement clock outputs

DIF_5

OUT

0.7V differential true clock outputs

OE_5

Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs

OE_6

Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs

DIF_6#

OUT

0.7V differential complement clock outputs

DIF_6

OUT

0.7V differential true clock outputs

VDD

PWR

Power supply, nominal 3.3V

GND

PWR

Ground pin.

DIF_7#

OUT

0.7V differential complement clock outputs

DIF_7

OUT

0.7V differential true clock outputs

OE_4

Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs

OE_7

Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs

LOCK

OUT

3.3V output indicating PLL Lock Status. This pin goes high when
lock is achieved.

IREF

This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.

GNDA

PWR

Ground pin for the PLL core.

VDDA

PWR

3.3V power for the PLL core.

Integrated
Circuit
Systems, Inc.

ICS9DB108

0723D--01/08/04

ICS9DB108 follows the Intel DB400 Differential Buffer Specification. This buffer provides four SRC clocks for PCI-Express,
next generation I/O devices. ICS9DB108 is driven by a differential input pair from a CK409/CK410 main clock generator, such
as the ICS952601 or ICS954101. ICS9DB108 can run at speeds up to 200MHz. It provides ouputs meeting tight cycle-to-cycle
jitter (50ps) and output-to-output skew (50ps) requirements.

General Description

Block Diagram

STOP

LOGIC

SRC_IN

SRC_IN#

DIF(7:0)

CONTROL

LOGIC

HIGH_BW#

BYPASS#/PLL
SDATA
SCLK

SRC_STOP#
PD#

SPREAD

COMPATIBLE

PLL

IREF

OE(7:0)

SRC_DIV#

Integrated
Circuit
Systems, Inc.

ICS9DB108

0723D--01/08/04

Absolute Max

Symbol

Parameter

Min

Max

Units

VDD_A

3.3V Core Supply Voltage

4.6

VDD_In

3.3V Logic Supply Voltage

4.6

Input Low Voltage

GND-0.5

Input High Voltage

+0.5V

Storage Temperature

-65

150

Tambient

Ambient Operating Temp

°C

Tcase Case

Temperature

115

°C

ESD prot

Input ESD protection

human body model

2000

Electrical Characteristics - Input/Supply/Common Output Parameters

= 0 - 70°C; Supply Voltage V

= 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Input High Voltage

3.3 V +/-5%

+ 0.3

Input Low Voltage

3.3 V +/-5%

GND

- 0.3

0.8

Input High Current

= V

-5

IL1

= 0 V; Inputs with no pull-up

resistors

-5

IL2

= 0 V; Inputs with pull-up

resistors

-200

Operating Supply Current

DD3.3OP

Full Active, C

= Full load;

250

all diff pairs driven

all differential pairs tri-stated

Input Frequency

= 3.3 V

100/133
166/200

220

MHz

Pin Inductance

Logic Inputs

1.5

OUT

Output pin capacitance

PLL Bandwidth when

PLL_BW=0

MHz

PLL Bandwidth when

PLL_BW=1

MHz

Clk Stabilization

1,2

STAB

From V

Power-Up and after

input clock stabilization or de-

assertion of PD# to 1st clock

1,2

Modulation Frequency

Triangular Modulation

kHz

Tdrive_SRC_STOP#

DIF output enable after

SRC_Stop# de-assertion

1,3

Tdrive_PD#

DIF output enable after

PD# de-assertion

300

1,3

Tfall

Fall time of PD# and

SRC_STOP#

Trise

Rise time of PD# and

SRC_STOP#

Guaranteed by design and characterization, not 100% tested in production.

See timing diagrams for timing requirements.

DD3.3PD

Time from deassertion until outputs are >200 mV

Input Capacitance

Input Low Current

Powerdown Current

PLL Bandwidth

Integrated
Circuit
Systems, Inc.

ICS9DB108

0723D--01/08/04

Electrical Characteristics - DIF 0.7V Current Mode Differential Pair

= 0 - 70°C; V

= 3.3 V +/-5%; C

=2pF, R

=33.2

, R

=49.9

REF

= 475

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

Current Source Output

Impedance

= V

3000

Voltage High

VHigh

660

850

1,3

Voltage Low

VLow

-150

150

1,3

Max Voltage

Vovs

1150

Min Voltage

Vuds

-300

Crossing Voltage (abs) Vcross(abs)

250

550

Crossing Voltage (var)

d-Vcross

Variation of crossing over all

edges

140

Long Accuracy

ppm

see Tperiod min-max values

ppm

1,2

200MHz nominal

4.9985

5.0015

200MHz spread

4.9985

5.0266

166.66MHz nominal

5.9982

6.0018

166.66MHz spread

5.9982

6.0320

133.33MHz nominal

7.4978

7.5023

133.33MHz spread

7.4978

5.4000

100.00MHz nominal

9.9970

10.0030

100.00MHz spread

9.9970

10.0533

200MHz nominal

4.8735

1,2

166.66MHz nominal/spread

5.8732

1,2

133.33MHz nominal/spread

7.3728

1,2

100.00MHz nominal/spread

9.8720

1,2

Rise Time

= 0.175V, V

= 0.525V

175

700

Fall Time

= 0.525V V

= 0.175V

175

700

Rise Time Variation

d-t

125

Fall Time Variation

d-t

125

Duty Cycle

Measurement from differential

wavefrom

Skew

sk3

= 50%

PLL mode,

Measurement from differential

wavefrom

BYPASS mode as additive jitter

Guaranteed by design and characterization, not 100% tested in production.

REF

= V

/(3xR

). For R

= 475

(1%), I

REF

= 2.32mA. I

= 6 x I

REF

and V

= 0.7V @ Z

=50

Statistical measurement on single

ended signal using oscilloscope

math function.

Measurement on single ended

signal using absolute value.

All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock

complies with CK409/CK410 accuracy requirements

Tperiod

Average period

Absolute min period

absmin

Jitter, Cycle to cycle

jcyc-cyc

Integrated
Circuit
Systems, Inc.

ICS9DB108

0723D--01/08/04

General SMBus serial interface information for the ICS9DB108

How to Write:

Controller (host) sends a start bit.

· Controller (host) sends the write address DC

(H)

· ICS clock will

acknowledge

· Controller (host) sends the begining byte location = N
· ICS clock will

acknowledge

· Controller (host) sends the data byte count = X
· ICS clock will

acknowledge

· Controller (host) starts sending

Byte N through

Byte N + X -1
(see Note 2)

· ICS clock will

acknowledge each byte one at a time

· Controller (host) sends a Stop bit

How to Read:

· Controller (host) will send start bit.
· Controller (host) sends the write address DC

(H)

· ICS clock will

acknowledge

· Controller (host) sends the begining byte

location = N

· ICS clock will

acknowledge

· Controller (host) will send a separate start bit.
· Controller (host) sends the read address DD

(H)

· ICS clock will

acknowledge

· ICS clock will send the data byte count = X
· ICS clock sends

Byte N + X -1

· ICS clock sends

Byte 0 through byte X (if X

(H)

was written to byte 8)

· Controller (host) will need to acknowledge each byte
· Controllor (host) will send a not acknowledge bit
· Controller (host) will send a stop bit

ICS (Sla ve /Re ce ive r)

W R

ACK

stoP bit

X Byte

Index Block Write Operation

S lave Address DC

(H )

B eginning Byte = N

W Rite

starT bit

Controlle r (Host)

Byte N + X - 1

Data Byte Count = X

B eginning Byte N

starT bit

W R

W Rite

Repeat starT

ReaD

Beginning B yte N

Byte N + X - 1

Not acknowledge

stoP bit

ICS (Sla ve /Re ce ive r)

Controlle r (Host)

X Byte

ACK

Data Byte Count = X

ACK

S lave Address DD

(H )

Index Block Read Operation

S lave Address DC

(H )

B eginning Byte = N

ACK

Integrated
Circuit
Systems, Inc.

ICS9DB108

0723D--01/08/04

SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)

Pin #

Name

Control Function Type

PWD

Bit 7

driven

Hi-Z

Bit 6

driven

Hi-Z

Bit 5

Bit 4

Bit 3

Bit 2

High BW

Low BW

Bit 1

fan-out

ZDB

Bit 0

x/2

SMBus Table: Output Control Register

Pin #

Name

Control Function Type

PWD

Bit 7

DIF_7

Output Control

Disable

Enable

Bit 6

DIF_6

Output Control

Disable

Enable

Bit 5

DIF_5

Output Control

Disable

Enable

Bit 4

DIF_4

Output Control

Disable

Enable

Bit 3

DIF_3

Output Control

Disable

Enable

Bit 2

DIF_2

Output Control

Disable

Enable

Bit 1

DIF_1

Output Control

Disable

Enable

Bit 0

DIF_0

Output Control

Disable

Enable

Byte 0

PD# drive mode

SRC_Stop# drive mode

Reserved

PLL_BW# adjust

BYPASS#/PLL

SRC_DIV#

Byte 1

42,41
38,37
34,33
30,29
20,21
16,17
12,13

8,9

Integrated
Circuit
Systems, Inc.

ICS9DB108

0723D--01/08/04

SMBus Table: Output Control Register

Pin #

Name

Control Function Type

PWD

Bit 7

DIF_7

Output Control

Bit 6

DIF_6

Output Control

Free-run Stoppable

Bit 5

DIF_5

Output Control

Free-run Stoppable

Bit 4

DIF_4

Output Control

Bit 3

DIF_3

Output Control

Bit 2

DIF_2

Output Control

Free-run Stoppable

Bit 1

DIF_1

Output Control

Free-run Stoppable

Bit 0

DIF_0

Output Control

SMBus Table: Output Control Register

Pin #

Name

Control Function Type

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: Vendor & Revision ID Register

Pin #

Name

Control Function Type

PWD

Bit 7

RID3

Bit 6

RID2

Bit 5

RID1

Bit 4

RID0

Bit 3

VID3

Bit 2

VID2

Bit 1

VID1

Bit 0

VID0

Byte 2

42,41

38,37

34,33

30,29
20,21

16,17

Reserved

12,13

8,9

Byte 3

Reserved

Byte 4

REVISION ID

-
-
-
-

VENDOR ID

-
-
-

Reserved

Reserved
Reserved

Integrated
Circuit
Systems, Inc.

ICS9DB108

0723D--01/08/04

SMBus Table: DEVICE ID

Pin #

Name

Control Function Type

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: Byte Count Register

Pin #

Name

Control

Function

Type

PWD

Bit 7

BC7

Bit 6

BC6

Bit 5

BC5

Bit 4

BC4

Bit 3

BC3

Bit 2

BC2

Bit 1

BC1

Bit 0

BC0

-
-
-
-

Byte 5

-
-
-

Byte 6

Writing to this

how many bytes

will be read back.

-
-
-
-
-
-
-

Device ID 6

Reserved

Device ID 7 (MSB)

Reserved

Device ID 5

Reserved

Device ID 4

Reserved

Device ID 3

Reserved

Device ID 0

Reserved

Device ID 2

Reserved

Device ID 1

Reserved

Integrated
Circuit
Systems, Inc.

ICS9DB108

0723D--01/08/04

The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before
shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering
down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending
on the PD# drive mode and Output control bits) before the PLL is shut down.

PD#, Power Down

When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending
on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode
bit is set to `0', all clock outputs will be held with DIF driven High with 2 x I

REF

and DIF# tri-stated. If the PD# drive mode bit is

set to `1', both DIF and DIF# are tri-stated.

PD# Assertion

Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set
to `1', all the DIF outputs must driven to a voltage of >200 mV within 300 ms of PD# de-assertion.

PD# De-assertion

PWRDWN#

DIF

DIF#

PWRDWN#

DIF

DIF#

Tstable

<1mS

Tdrive_PwrDwn#

<300uS, >200mV

Integrated
Circuit
Systems, Inc.

ICS9DB108

0723D--01/08/04

Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the SRC_STOP# drive bit is `0', the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xI

REF.

DIF# is not driven, but pulled low by the termination. When the

SRC_STOP# drive bit is `1', the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.

SRC_STOP# - Assertion

All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is
2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is `1' (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.

SRC_STOP# - De-assertion (transition from '0' to '1')

The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.

SRC_STOP#

PWRDWN#

SRC_Stop#

DIF (Free Running)

DIF# (Free Running)

DIF (Stoppable)

DIF# (Stoppable)

1mS

PWRDWN#

SRC_Stop#

DIF (Free Running)

DIF# (Free Running)

DIF (Stoppable)

DIF# (Stoppable)

1mS

SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)

SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)

Integrated
Circuit
Systems, Inc.

ICS9DB108

0723D--01/08/04

INDEX
AREA

1 2

h x 45°

SEATING
PLANE

- C -

.10 (.004) C

MIN

MAX

MIN

MAX

2.41

2.80

.095

.110

0.20

0.40

.008

.016

0.20

0.34

.008

.0135

0.13

0.25

.005

.010

10.03

10.68

.395

.420

7.40

7.60

.291

.299

e
h

0.38

0.64

.015

.025

0.50

1.02

.020

.040

0°

8°

0°

8°

MIN

MAX

MIN

MAX

15.75

16.00

.620

.630

10-0034

SYMBOL

In Millimeters

In Inches

COMMON DIMENSIONS

SEE VARIATIONS

0.635 BASIC

0.025 BASIC

Reference Doc.: JEDEC Publication 95, MO-118

VARIATIONS

SEE VARIATIONS

D mm.

D (inch)

Ordering Information

ICS9DB108yFLFT

Example:

Designation for tape and reel packaging
Lead Free (optional)

Package Type
F = SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Prefix
ICS, AV = Standard Device

ICS XXXX y F LF T

Integrated
Circuit
Systems, Inc.

ICS9DB108

0723D--01/08/04

INDEX

AREA

INDEX

AREA

1 2

SEATING

PLANE

SEATING

PLANE

- C -

aaa

MIN

MAX

MIN

MAX

1.20

.047

0.05

0.15

.002

.006

0.80

1.05

.032

.041

0.17

0.27

.007

.011

0.09

0.20

.0035

.008

6.00

6.20

.236

.244

e
L

0.45

0.75

.018

.030

0°

8°

0°

8°

aaa

0.10

.004

VARIATIONS

MIN

MAX

MIN

MAX

12.40

12.60

.488

.496

10-0039

Reference Doc.: JEDEC Publication 95, MO-153

In Millimeters

In Inches

COMMON DIMENSIONS

0.50 BASIC

0.020 BASIC

8.10 BASIC

0.319 BASIC

D (inch)

SEE VARIATIONS

D mm.

48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP

(240 mil) (20 mil)

SYMBOL

SEE VARIATIONS

COMMON DIMENSIONS

SEE VARIATIONS

Ordering Information

ICS9DB108yGLFT

Example:

Designation for tape and reel packaging
Lead Free (optional)

Package Type
G = TSSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Prefix
ICS, AV = Standard Device

ICS XXXX y G LF T

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ICS9DB108yGLFT