Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Ratio of Output Frequency to Input Frequency Function Table, FS0
- Ratio of Output Frequency to Input Frequency Function Table, FS1
- BYPASS Table
- Output Enable Function Table, nOE0
- Output Enable Function Table, nOE1
- PLL Bandwith Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- HCSL DC Characteristics
- AC Characteristics
- Typical Phase Noise Plot
- Parameter Measurement Information
- 3.3V HCSL Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Output Skew Diagram
- Cycled-to-Cycle Jitter Diagram
- HCSL Output Rise/Fall Time Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Application Information
- Power Supply Filtering Techniques
- Wiring the Differential Input to Accept Single Ended Levels
- Differential Clock Input Interface
- Reliability Information
- Transistor Count
- Package Outline for TSSOP
- Pakcage Dimensions for TSSOP
- Package Outline for SSOP
- Package Dimensions for SSOP
- Ordering Information
9DB202CG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 6, 2004
1
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI E
XPRESS
TM
J
ITTER
A
TTENUATOR
G
ENERAL
D
ESCRIPTION
The ICS9DB202 is a high perfromance 1-to-2 Dif-
ferential-to-HCSL Jitter Attenuator designed for use
in PCI ExpressTM systems. In some PCI ExpressTM
systems, such as those found in desktop PCs, the
PCI ExpressTM clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In these
systems, a jitter-attenuating device may be necessary in order
to reduce high frequency random and deterministic jitter com-
ponents from the PLL synthesizer and from the system board.
The ICS9DB202 has two PLL bandwidth modes. In low band-
width mode, the PLL loop bandwidth is 500kHz. This setting of-
fers the best jitter attenuation and is still high enough to pass a
triangular input spread spectrum profile. In high bandwidth mode,
the PLL bandwidth is at 1MHz and allows the PLL to pass more
spread spectrum modulation.
For serdes which have x10 reference multipliers instead of x12.5
multipliers, each of the two PCI ExpressTM outputs (PCIEX0:1)
can be set for 125MHz instead of 100MHz by configuring the
appropriate frequency select pins (FS0:1).
Features
Two 0.7V current mode differential HCSL output pairs
1 differential clock input
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 140MHz
Output skew: 110ps (maximum)
Cycle-to-cycle jitter: 110ps (maximum)
RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):
2.42ps (typical)
3.3V operating supply
0C to 70C ambient operating temperature
Lead-Free package available
Industrial temperature information available upon request
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
nOE0
nCLK
CLK
BYPASS
nOE1
PCIEXT0
nPCIEXC0
PCIEXT1
nPCIEXC1
B
LOCK
D
IAGRAM
ICS9DB202
20-Lead TSSOP
6.50mm x 4.40mm x 0.92
package body
G Package
Top View
ICS9DB202
20-Lead, 209-MIL SSOP
5.30mm x 7.20mm x 1.75mm
body package
F Package
Top View
Phase
Detector
VCO
Loop
Filter
1 HiZ
0 Enabled
1 HiZ
0 Enabled
0 4
1 5
0 5
1 4
FS0
FS1
Internal Feedback
5
Current
Set
-
+
0
1
0
1
IREF
PLL_BW
CLK
nCLK
FS0
V
DD
GND
PCIEXT0
PCIEXC0
V
DD
nOE0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DDA
BYPASS
IREF
FS1
V
DD
GND
PCIEXT1
PCIEXC1
V
DD
nOE1
9DB202CG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 6, 2004
2
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI E
XPRESS
TM
J
ITTER
A
TTENUATOR
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
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(
9DB202CG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 6, 2004
3
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI E
XPRESS
TM
J
ITTER
A
TTENUATOR
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
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Y
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S
F
,
1
E
O
n
,
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E
O
n
V
D
D
V
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I
V
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6
4
.
3
=
0
5
1
A
W
B
_
L
L
P
,
0
S
F
5
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
,
S
S
A
P
Y
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S
F
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1
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n
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0
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O
n
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D
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,
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5
6
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3
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N
I
V
0
=
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-
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W
B
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L
L
P
,
0
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F
0
5
1
-
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
20 Lead TSSOP
73.2C/W (0 lfpm)
20 Lead SSOP
80.8C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
9DB202CG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 6, 2004
4
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI E
XPRESS
TM
J
ITTER
A
TTENUATOR
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= 0C
TO
70C, RREF = 475
T
ABLE
4D. HCSL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= 0C
TO
70C, RREF = 475
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9DB202CG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 6, 2004
5
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI E
XPRESS
TM
J
ITTER
A
TTENUATOR
T
YPICAL
P
HASE
N
OISE
AT
100MH
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
100MHz
RMS Phase Jitter (Random)
1.5MHz to 22MHz = 2.42ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
PCI ExpressTM Filter to raw data
PCI ExpressTM Filter
The illustrated phase noise plot was taken using a low phase
noise signal generator, the noise floor of the signal generator is
less than that of the device under test.
Using this configuration allows one to see the true spectral purity
or phase noise performance of the PLL in the device under test.
Due to the tracking ability of a PLL, it will track the input signal
up to its loop bandwidth. Therefore, if the input phase noise is
greater than that of the PLL, it will increase the output phase
noise performance of the device. It is recommended that the
phase noise performance of the input is verified in order to
achieve the above phase noise performance.
Raw Phase Noise Data
9DB202CG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 6, 2004
6
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI E
XPRESS
TM
J
ITTER
A
TTENUATOR
SCOPE
Qx
HCSL
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
S
KEW
D
IFFERENTIAL
I
NPUT
L
EVEL
3.3V HCSL O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
0V
C
YCLE
-
TO
-C
YCLE
J
ITTER
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
3.3V5%
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
V
DD
tsk(o)
PCIEXCx
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
PCIEXTy
PCIEXCx
PCIEXTy
HCSL O
UTPUT
R
ISE
/F
ALL
T
IME
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
PCIEXT0,
PCIEXT1
PCIEXC0,
PCIEXC1
V
DD,
V
DDA
GND
PCIEXT0,
PCIEXT1
PCIEXC0,
PCIEXC1
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
9DB202CG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 6, 2004
7
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI E
XPRESS
TM
J
ITTER
A
TTENUATOR
A
PPLICATION
I
NFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS9DB202 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL. V
DD
and V
DDA
should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required.
Figure 1 illus-
trates how a 24
resistor along with a 10F and a .01F by-
pass capacitor should be connected to each V
DDA
pin.
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
24
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
9DB202CG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 6, 2004
8
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI E
XPRESS
TM
J
ITTER
A
TTENUATOR
F
IGURE
3C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 3A to 3D show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
3A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
9DB202CG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 6, 2004
9
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI E
XPRESS
TM
J
ITTER
A
TTENUATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS9DB202 is: 2471
T
ABLE
6A.
JA
VS
. A
IR
F
LOW
T
ABLE
F
OR
20 L
EAD
TSSOP P
ACKAGE
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98C/W
88C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
6B.
JA
VS
. A
IR
F
LOW
T
ABLE
F
OR
20 L
EAD
SSOP P
ACKAGE
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
80.8C/W
73.2C/W
69.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
9DB202CG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 6, 2004
10
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI E
XPRESS
TM
J
ITTER
A
TTENUATOR
P
ACKAGE
O
UTLINE
- F S
UFFIX
FOR
20 L
EAD
SSOP
T
ABLE
6B. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-150
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
20 L
EAD
TSSOP
T
ABLE
6A. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
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9DB202CG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 6, 2004
11
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI E
XPRESS
TM
J
ITTER
A
TTENUATOR
T
ABLE
7. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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