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Электронный компонент: ICS9DB306BLLF

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9DB306BL
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
1
Integrated
Circuit
Systems, Inc.
ICS9DB306
PCI E
XPRESS
,
J
ITTER
A
TTENUATOR
G
ENERAL
D
ESCRIPTION
The ICS9DB306 is a high performance 1-to-6
Differential-to LVPECL Jitter Attenuator designed
for use in PCI ExpressTM systems. In some PCI
ExpressTM systems, such as those found in desktop
PCs, the PCI ExpressTM clocks are generated from
a low bandwidth, high phase noise PLL frequency
synthesizer. In these systems, a zero delay buffer may be
required to attenuate high frequency random and deterministic
jitter components from the PLL synthesizer and from the system
board. The ICS9DB306 has 2 PLL bandwidth modes. In low
bandwidth mode, the PLL loop BW is about 500kHz and this
setting will attenuate much of the jitter from the reference clock
input while being high enough to pass a triangular input spread
spectrum profile. There is also a high bandwidth mode which
sets the PLL bandwidth at 1MHz which will pass more spread
spectrum modulation.
For serdes which have x30 reference multipliers instead of x25
multipliers, 5 of the 6 PCI ExpressTM outputs (PCIEX1:5) can be
set for 125MHz instead of 100MHz by configuring the appropri-
ate frequency select pins (FS0:1). Output PCIEX0 will always
run at the reference clock frequency (usually 100MHz) in desk-
top PC PCI ExpressTM Applications.
Features
Six differential LVPECL output pairs
1 differential clock input
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 140MHz
Output skew: 135ps (maximum)
Cycle-to-Cycle jitter: 25ps (maximum)
RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):
3ps (typical)
3.3V operating supply
0C to 70C ambient operating temperature
Lead-Free package fully RoHS compliant
Industrial temperature information available upon request
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
nOE0
CLK
nCLK
BYPASS
nOE1
PCIEXT0
nPCIEXC0
PCIEXT1
nPCIEXC1
PCIEXT2
nPCIEXC2
PCIEXT3
nPCIEXC3
PCIEXT4
nPCIEXC4
PCIEXT5
nPCIEXC5
B
LOCK
D
IAGRAM
ICS9DB306
28-Lead TSSOP, 173-MIL
4.4mm x 9.7mm x 0.92mm
body package
L Package
Top View
V
EE
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
V
CC
nOE0
nOE1
V
CC
PCIEXC3
PCIEXT3
PCIEXC4
PCIEXT4
V
EE
V
CC
PCIEXC0
PCIEXT0
FS0
nCLK
CLK
PLL_BW
V
CCA
V
EE
BYPASS
FS1
PCIEXT5
PCIEXC5
V
CC
ICS9DB306
28-Lead, 209-MIL SSOP
5.3mm x 10.2mm x 1.75mm
body package
F Package
Top View
Phase
Detector
VCO
Loop
Filter
1 Disabled
0 Enabled
1 Disabled
0 Enabled
5
0 4
1 5
0 5
1 4
FS0
FS1
Internal Feedback
5
0
1
0
1
0
1
Buffer
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
background image
9DB306BL
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
2
Integrated
Circuit
Systems, Inc.
ICS9DB306
PCI E
XPRESS
,
J
ITTER
A
TTENUATOR
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
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background image
9DB306BL
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
3
Integrated
Circuit
Systems, Inc.
ICS9DB306
PCI E
XPRESS
,
J
ITTER
A
TTENUATOR
T
ABLE
4C. D
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A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
49.8C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
background image
9DB306BL
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
4
Integrated
Circuit
Systems, Inc.
ICS9DB306
PCI E
XPRESS
,
J
ITTER
A
TTENUATOR
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
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background image
9DB306BL
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
5
Integrated
Circuit
Systems, Inc.
ICS9DB306
PCI E
XPRESS
,
J
ITTER
A
TTENUATOR
T
YPICAL
P
HASE
N
OISE
AT
100MH
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
100MHz
RMS Phase Jitter (Random)
1.5MHz to 22MHz = 3ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
PCI ExpressTM Filter to raw data
PCI ExpressTM Filter
The illustrated phase noise plot was taken using a low phase
noise signal generator, the noise floor of the signal generator is
less than that of the device under test.
Using this configuration allows one to see the true spectral pu-
rity or phase noise performance of the PLL in the device under
test. Due to the tracking ability of a PLL, it will track the input
signal up to its loop bandwidth. Therefore, if the input phase noise
is greater than that of the VCO, it will increase the output phase
noise performance of the device. It is recommended that the
phase noise performance of the input is verified in order to
achieve the above phase noise performance.
Raw Phase Noise Data

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