Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
0823--04/02/04
Pin Configuration
Recommended Application:
Frequency Timing Generator for Differential CPU, PCI-Express
& SATA clocks
Features:
Generates common frequencies from 14.318 MHz or 25
MHz
Crystal or reference input
8 - 0.7V current-mode differential output pairs
Supports Serial-ATA at 100 MHz
Two spread spectrum modes: 0 to -0.5 downspread and
+/-0.25% centerspread
Unused inputs may be disabled in either driven or Hi-Z
state for power management.
Key Specifications:
Output cycle-to-cycle jitter < 85 ps
Output to output skew < 85 ps
+/-300 ppm frequency accuracy on output clocks
Programmable FTG for Differential P4
TM
CPU, PCI-Express & SATA Clocks
48-pin SSOP & TSSOP
Frequency Select Table
SEL14M_25M#
(FS3)
FS2 FS1 FS0 OUTPUT(MHz)
0
0
0
0
100.00
0
0
0
1
125.00
0
0
1
0
133.33
0
0
1
1
166.67
0
1
0
0
200.00
0
1
0
1
266.66
0
1
1
0
333.33
0
1
1
1
400.00
1
0
0
0
100.00
1
0
0
1
125.00
1
0
1
0
133.33
1
0
1
1
166.67
1
1
0
0
200.00
1
1
0
1
266.66
1
1
1
0
333.33
1
1
1
1
400.00
XIN/CLKIN
1
48 VDDA
X2
2
47 GNDA
VDD
3
46 IREF
GND
4
45 FS0
REFOUT
5
44 FS1
FS2
6
43 OE_0**
OE_7**
7
42 DIF_0
DIF_7
8
41 DIF_0#
DIF_7#
9
40 VDD
VDD 10
39 DIF_1
DIF_6 11
38 DIF_1#
DIF_6# 12
37 OE_1*
OE_6* 13
36 VDD
VDD 14
35 GND
GND 15
34 OE_2*
OE_5* 16
33 DIF_2
DIF_5 17
32 DIF_2#
DIF_5# 18
31 VDD
VDD 19
30 DIF_3
DIF_4 20
29 DIF_3#
DIF_4# 21
28 OE_3**
OE_4** 22
27 SEL14M_25M#
SDATA 23
26 SPREAD
SCLK 24
25 DIF_STOP#
Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors
Pin names followed by an '*' have 120 Kohm pull UP resistors
I
C
S
9
FG
108
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
Third party brands and names are the property of their respective owners
2
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
0823--04/02/04
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
XIN/CLKIN
IN
Crystal input or Reference Clock input
2
X2
OUT
Crystal output, Nominally 14.318MHz
3
VDD
PWR
Power supply, nominal 3.3V
4
GND
PWR
Ground pin.
5
REFOUT
IN
Reference Clock output
6
FS2
IN
Frequency select pin.
7
OE_7**
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
8
DIF_7
OUT
0.7V differential true clock outputs
9
DIF_7#
OUT
0.7V differential complement clock outputs
10
VDD
PWR
Power supply, nominal 3.3V
11
DIF_6
OUT
0.7V differential true clock outputs
12
DIF_6#
OUT
0.7V differential complement clock outputs
13
OE_6*
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
14
VDD
PWR
Power supply, nominal 3.3V
15
GND
PWR
Ground pin.
16
OE_5*
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
17
DIF_5
OUT
0.7V differential true clock outputs
18
DIF_5#
OUT
0.7V differential complement clock outputs
19
VDD
PWR
Power supply, nominal 3.3V
20
DIF_4
OUT
0.7V differential true clock outputs
21
DIF_4#
OUT
0.7V differential complement clock outputs
22
OE_4**
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
23
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
24
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors
Pin names followed by '*' have 120 Kohm pull UP resistors
3
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
0823--04/02/04
Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
25
DIF_STOP#
IN
Active low input to stop differential output clocks.
26
SPREAD
IN
Asynchronous, active high input to enable spread spectrum
functionality.
27
SEL14M_25M#
IN
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818
MHz, 0 = 25 MHz
28
OE_3**
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
29
DIF_3#
OUT
0.7V differential complement clock outputs
30
DIF_3
OUT
0.7V differential true clock outputs
31
VDD
PWR
Power supply, nominal 3.3V
32
DIF_2#
OUT
0.7V differential complement clock outputs
33
DIF_2
OUT
0.7V differential true clock outputs
34
OE_2*
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
35
GND
PWR
Ground pin.
36
VDD
PWR
Power supply, nominal 3.3V
37
OE_1*
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
38
DIF_1#
OUT
0.7V differential complement clock outputs
39
DIF_1
OUT
0.7V differential true clock outputs
40
VDD
PWR
Power supply, nominal 3.3V
41
DIF_0#
OUT
0.7V differential complement clock outputs
42
DIF_0
OUT
0.7V differential true clock outputs
43
OE_0**
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
44
FS1
IN
Frequency select pin.
45
FS0
IN
Frequency select pin.
46
IREF
OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied
to ground in order to establish the appropriate current. 475 ohms is
the standard value.
47
GNDA
PWR
Ground pin for the PLL core.
48
VDDA
PWR
3.3V power for the PLL core.
Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors
Pin names followed by '*' have 120 Kohm pull UP resistors
4
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
0823--04/02/04
ICS9FG108 is a Frequency Timing Generator that provides 8 differential output pairs that are compliant to the Intel CK410
specification. It also provides support for PCI-Express, next generation I/O, and SATA. The part synthesizes several output
frequencies from either a 14.31818 Mhz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock
instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 85 ps and output-to-output skew of less than 85 ps.
ICS9FG108 also provides a copy of the reference clock. Frequency selection can be accomplished via strap pins or SMBus
control.
General Description
Block Diagram
Power Groups
VDD
GND
3
4
10,14,19,31,36,40
15,35
N/A
47
48
47
IREF
Analog VDD & GND for PLL Core
Description
Pin Number
REFOUT, Digital Inputs, SMBus
DIF Outputs
STOP
LOGIC
XIN/CLKIN
X2
DIF(7:0)
CONTROL
LOGIC
SPREAD
FS(2:0)
SDATA
SCLK
SEL14M_25M#
DIF_STOP#
PROGRAMMABLE
SPREAD PLL
4
IREF
OSC
R EF OU T
OE(7:0)
5
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
0823--04/02/04
Absolute Max
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
V
DD
+ 0.5V
V
VDD_In
3.3V Logic Input Supply Voltage
GND - 0.5
V
DD
+ 0.5V
V
Ts
Storage Temperature
-65
150
C
Tambient
Ambient Operating Temp
0
70
C
Tcase Case
Temperature
115
C
ESD prot
Input ESD protection
human body model
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
V
IH
3.3 V +/-5%
2
V
DD
+ 0.3
V
Input Low Voltage
V
IL
3.3 V +/-5%
V
SS
- 0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
-5
5
uA
I
IL1
V
IN
= 0 V; Inputs with no pull-
up resistors
-5
uA
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200
uA
Full Active, C
L
= Full load;
f = 400 MHz
250
mA
Full Active, C
L
= Full load;
f = 100 MHz
200
mA
Input Frequency
3
F
i
V
DD
= 3.3 V
14
25
MHz
3
Pin Inductance
1
L
pin
7
nH
1
C
IN
Logic Inputs
1.5
5
pF
1
C
OUT
Output pin capacitance
6
pF
1
Clk Stabilization
1,2
T
STAB
From V
DD
Power-Up and after
input clock stabilization to 1st
clock
1.8
ms
1,2
Modulation Frequency
f
MOD
Triangular Modulation
30
40
kHz
1
DIF output enable
t
DIFOE
DIF output enable after
DIF_Stop# de-assertion
10
ns
1
Input Rise and Fall times
t
R
/t
F
20% to 80% of VDD
5
ns
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet
ppm frequency accuracy on PLL outputs.
Input/Output
Capacitance
1
Input Low Current
I
DD3.3OP
Operating Supply Current
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