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Электронный компонент: ICSSSTUF32864A

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Integrated
Circuit
Systems, Inc.
ICSSSTUF32864A
0987B--09/28/04
Recommended Application:
DDR2 Memory Modules
Provides complete DDR DIMM solution with
ICS97U877
Ideal for DDR2 400, 533 and 667
Product Features:
25-bit 1:1 or 14-bit 1:2 configurable registered buffer
Supports SSTL_18 JEDEC specification on data
inputs and outputs
Supports LVCMOS switching levels on C0, C1 and
RESET# inputs
Low voltage operation
V
DD
= 1.7V to 1.9V
Available in 96 BGA package
Drop-in replacement for ICSSSTUF32866
Green packages available
25-Bit Configurable Registered Buffer for DDR2
Truth Table
Pin Configuration
96 Ball BGA
(Top View)
Ball Assignments
A
B
1
2
3
4
5
6
C
D
E
F
G
H
J
K
L
M
N
P
R
T
A
DCKE
NC
V
REF
V
DD
QCKE
NC
B
D2
D15
GND
GND
Q2
Q15
C
D3
D16
V
DD
V
DD
Q3
Q16
D
DODT
NC
GND
GND
QODT
NC
E
D5
D17
V
DD
V
DD
Q5
Q17
F
D6
D18
GND
GND
Q6
Q18
G
NC
RST#
V
DD
V
DD
C1
C0
H
CK
DCS#
GND
GND
QCS#
NC
J
CK#
CSR#
V
DD
V
DD
ZOH
ZOL
K
D8
D19
GND
GND
Q8
Q19
L
D9
D20
V
DD
V
DD
Q9
Q20
M
D10
D21
GND
GND
Q10
Q21
N
D11
D22
V
DD
V
DD
Q11
Q22
P
D12
D23
GND
GND
Q12
Q23
R
D13
D24
V
DD
V
DD
Q13
Q24
T
D14
D25
V
REF
V
DD
Q14
Q25
1
2
3
4
5
6
1:1 Register (C0 = 0, C1 = 0)
I nputs
Outputs
RST#
DCS#
CSR#
CK
CK#
Dn,
DODT,
DCK E
Qn
QCS#
QODT,
QCKE
H
L
L
L
L
L
L
H
L
L
H
H
L
H
H
L
L
L or H
L or H
X
Q
0
Q
0
Q
0
H
L
H
L
L
L
L
H
L
H
H
H
L
H
H
L
H
L or H
L or H
X
Q
0
Q
0
Q
0
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L or H
L or H
X
Q
0
Q
0
Q
0
H
H
H
L
Q
0
H
L
H
H
H
H
Q
0
H
H
H
H
H
L or H
L or H
X
Q
0
Q
0
Q
0
L
X or
Floating
X or
Floating
X or
Floating
X or
Floating
X or
Floating
L
L
L
2
ICSSSTUF32864A
0987B--09/28/04
Ball Assignments
1:2 Register A (C0 = 0, C1 = 1)
Ball Assignments
1:2 Register B (C0 = 1, C1 = 1)
A
DCKE
NC
V
REF
V
DD
QCKEA
QCKEB
B
D2
NC
GND
GND
Q2A
Q2B
C
D3
NC
V
DD
V
DD
Q3A
Q3B
D
DODT
NC
GND
GND
QODTA
QODTB
E
D5
NC
V
DD
V
DD
Q5A
Q5B
F
D6
NC
GND
GND
Q6A
Q6B
G
NC
RST#
V
DD
V
DD
C1
C0
H
CK
DCS#
GND
GND
QCSA#
QCSB#
J
CK#
CSR#
V
DD
V
DD
ZOH
ZOL
K
D8
NC
GND
GND
Q8A
Q8B
L
D9
NC
V
DD
V
DD
Q9A
Q9B
M
D10
NC
GND
GND
Q10A
Q10B
N
D11
NC
V
DD
V
DD
Q11A
Q11B
P
D12
NC
GND
GND
Q12A
Q12B
R
D13
NC
V
DD
V
DD
Q13A
Q13B
T
D14
NC
V
REF
V
DD
Q14A
Q14B
1
2
3
4
5
6
A
D1
NC
V
REF
V
DD
Q1A
Q1B
B
D2
NC
GND
GND
Q2A
Q2B
C
D3
NC
V
DD
V
DD
Q3A
Q3B
D
D4
NC
GND
GND
Q4A
Q4B
E
D5
NC
V
DD
V
DD
Q5A
Q5B
F
D6
NC
GND
GND
Q6A
Q6B
G
NC
RST#
V
DD
V
DD
C1
C0
H
CK
DCS#
GND
GND
QCSA#
QCSB#
J
CK#
CSR#
V
DD
V
DD
ZOH
ZOL
K
D8
NC
GND
GND
Q8A
Q8B
L
D9
NC
V
DD
V
DD
Q9A
Q9B
M
D10
NC
GND
GND
Q10A
Q10B
N
DODT
NC
V
DD
V
DD
QODTA
QODTB
P
D12
NC
GND
GND
Q12A
Q12B
R
D13
NC
V
DD
V
DD
Q13A
Q13B
T
DCKE
NC
V
REF
V
DD
QCKEA
QCKEB
1
2
3
4
5
6
General Description
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUF32864A operates
from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going low.
The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when
high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).
The device supports low-power standby operation. When the reset input (RST#) is low, the differential input receivers
are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when
RST# is low all registers are reset, and all outputs are forced low. The LVCMOS RST# and Cn inputs must always be
held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied,
RST# must be held in the low state during power up.
In the DDR-II RDIMM application, RST# is specified to be completely asynchronous with respect to CK and CK#.
Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared
and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers.
As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST# until
the input receivers are fully enabled, the design of the ICSSSTUF32864A must ensure that the outputs will remain
low, thus ensuring no glitches on the output.
The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS#
and CSR# inputs are high. If either DCS# or CSR# input is low, the Qn outputs will function normally. The RST input
has priority over the DCS# and CSR# control and will force the outputs low. If the DCS#-control functionality is not
desired, then the CSR# input can be hardwired to ground, in which case, the setup-time requirement for DCS# would
be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC).
3
ICSSSTUF32864A
0987B--09/28/04
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Ball Assignment
4
ICSSSTUF32864A
0987B--09/28/04
Block Diagram for 1:1 mode (positive logic)
D
C1
R
QCKEA
RST#
CK
CK#
V
REF
DODT
To 21 Other Channels
1D
C1
R
QCSA#
DCS#
1D
C1
R
Q1A
D1
Q1B
*
0
1
D
C1
R
QODTA
DCKE
CSR#
*Note: Disabled in 1:1 configuration
5
ICSSSTUF32864A
0987B--09/28/04
Block Diagram for 1:2 mode (positive logic)
1D
C1
R
QCKEA
RST#
CK
CK#
V
REF
DODT
To 10 Other Channels
QCKEB*
1D
C1
R
QCSA#
DCS#
QCSB#*
1D
C1
R
Q1A
D1
Q1B
*
0
1
1D
C1
R
QODTA
DCKE
QODTB*
CSR#
*Note: Disabled in 1:1 configuration