www.docs.chipfind.ru
Integrated
Circuit
Systems, Inc.
ICSSSTV16859
Third party brands and names are the property of their respective owners.
16859 Rev B 06/22/01
Recommended Application:
DDR Memory Modules
Product Features:
Differential clock signals
Meets SSTL_2 signal data
Supports SSTL_2 class II specifications on outputs
low-voltage operation
- VDD = 2.3V to 2.7V
Available in 64 pin TSSOP and 56 pin MLF2 packages
DDR 13-Bit to 26-Bit Registered Buffer
Truth Table
1
Block Diagram
Notes:
1.
H = High Signal Level
L = Low Signal Level
= Transition LOW-to-HIGH
= Transition HIGH -to LOW
X = Irrelevant
2.
Output level before the indicated
steady state input conditions were
established.
CLK
CLK#
48
49
51
35
45
D1
VREF
RESET#
To 12 Other Channels
Q1A
Q1B
16
32
CLK
R
D1
s
t
u
p
n
I
s
t
u
p
t
u
O
Q
#
T
E
S
E
R
K
L
C
#
K
L
C
D
Q
L
r
o
X
g
n
i
t
a
o
l
F
r
o
X
g
n
i
t
a
o
l
F
r
o
X
g
n
i
t
a
o
l
F
L
H
H
H
H
L
L
H
H
r
o
L
H
r
o
L
X
Q
0
)
2
(
Preliminary Product Preview
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
56 pin MLF2
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
1
14
15
28
29
43
42
56
D10
D9
D8
D7
RB
GND
CLKB
CLK
VDDQ
VDDI
VREF
D6
D5
D4
Q8A
VDDQ
Q9A
Q10A
Q11A
Q12A
Q13A
VDDQ
GND
D13
D12
VDDI
VDDQ
D11
Q7B
Q6B
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
VDDQ
D1
D2
VDDI
VDDQ
D3
ICSSTV16859
Pin Configurations
64-Pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
Q7B
Q6B
GND
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
VDDQ
GND
D13
D12
VDD
VDDQ
GND
D11
D10
D9
GND
D8
D7
RESET#
GND
CLK#
CLK
VDDQ
VDD
VREF
D6
GND
D5
D4
D3
GND
VDDQ
VDD
D2
D1
GND
VDDQ
ICSSSTV16859
6.10 mm. Body, 0.50 mm. pitch
2
ICSSSTV16859
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
General Description
Pin Configuration
The 13-bit to 26-bit ICSSTV16859 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2
I/O Levels except for the RESET# input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the
positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supported with LVCMOS
levels as VREF may not be stable during power-up. RESET# is asynchronous and is intended for power-up only and
when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and
clock are switched off.
The ICSSSTV16859 supports low-power standby operation. When RESET# is LOW, the differential input receivers
are disabled, and are allowed. In addition, when RESET# is LOW, all registers are reset, and all outputs are forced
LOW. The LVCMOS RESET# input must always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the
LOW state during power up.
In the DDR DIMM application RESET# is specified to be completely asynchronous with respect to CK and CK#.
Therefore, no timing relationship can be guaranteed between the two. When entering RESET#, the register will be
cleared and the outputs will be driven LOW quickly, relative to the time to disable the differential input receivers,
thus ensuring no glitches on the output. However, when coming out of RESET#, the register will become active
quickly, relative to the time to enable the differential input receivers. When the data inputs are LOW, and the clock
is stable, during the time from the LOW-to-HIGH transition of RESET# until the input receivers are fully enabled, the
design must ensure that the outputs will remain LOW.
E
M
A
N
N
I
P
E
P
Y
T
N
O
I
T
P
I
R
C
S
E
D
)
1
:
3
1
(
Q
T
U
P
T
U
O
t
u
p
t
u
o
a
t
a
D
D
N
G
R
W
P
d
n
u
o
r
G
Q
D
D
V
R
W
P
l
a
n
i
m
o
n
V
5
.
2
,
e
g
a
t
l
o
v
y
l
p
p
u
s
t
u
p
t
u
O
)
1
:
3
1
(
D
T
U
P
N
I
t
u
p
n
i
a
t
a
D
K
L
C
T
U
P
N
I
t
u
p
n
i
k
c
o
l
c
r
e
t
s
a
m
e
v
i
t
i
s
o
P
#
K
L
C
T
U
P
N
I
t
u
p
n
i
k
c
o
l
c
r
e
t
s
a
m
e
v
i
t
a
g
e
N
D
D
V
R
W
P
l
a
n
i
m
o
n
V
5
.
2
,
e
g
a
t
l
o
v
y
l
p
p
u
s
e
r
o
C
#
T
E
S
E
R
T
U
P
N
I
)
w
o
l
e
v
i
t
c
a
(
t
e
s
e
R
F
E
R
V
T
U
P
N
I
l
a
n
i
m
o
n
V
5
.
2
,
e
g
a
t
l
o
v
e
c
n
e
r
e
f
e
r
t
u
p
n
I
D
A
P
r
e
t
n
e
C
R
W
P
)
y
l
n
o
e
g
a
k
c
a
p
2
F
L
M
(
d
n
u
o
r
G
3
ICSSSTV16859
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V
Input Voltage
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.5 to VDD +0.5
Output Voltage
1,2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.5 to VDDQ +0.5
Input Clamp Current . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . . . 50mA
Continuous Output Current . . . . . . . . . . . . . . . . . 50mA
VDD, VDDQ or GND Current/Pin . . . . . . . . . . . . 100mA
Package Thermal Impedance
3
. . . . . . . . . . . . . . . . . . . .
55C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Notes:
1. The input and output negative voltage
ratings may be excluded if the input
and output clamp ratings are observed.
2. This current will flow only when the
output is in the high state level
V
0
>V
DDQ
.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Recommended Operating Conditions
PARAM ETER
M IN
TYP
M AX
UNITS
V
DD
2.3
2.5
2.7
V
DDQ
2.3
2.5
2.7
V
REF
1.15
1.25
1.35
V
TT
V
REF
-0.04
V
REF
V
REF
-0.04
V
I
Input Voltage
0
V
DD
V
IH
DC Input High Voltage
V
REF
+0.15
V
IH
AC Input High Voltage
V
REF
+0.31
V
IL
DC Input Low Voltage
V
REF
-0.15
V
IL
AC Input Low Voltage
V
REF
-0.31
V
IH
Input High Voltage Level
1.7
V
IL
Input Low Voltage Level
0.7
V
ICR
Common mode Input Range
0.97
1.53
V
ID
Differential Input Voltage
0.36
V
IX
(V
DDQ
/2) -0.2
(V
DDQ
/2)
+0.2
I
OH
-20
I
OL
20
T
A
0
70
C
1
Guarenteed by design, not 100% tested in production.
Operating Free-Air Temperature
RESET#
CLK, CLK#
V
Termination Voltage
Cross Point Voltage of Differential Clock
Pair
High-Level Output Current
Low-Level Output Current
Data Inputs
mA
DESCRIPTION
Supply Voltage
I/O Supply Voltage
Reference Voltage V
REF
= 0.5X V
DDQ
4
ICSSSTV16859
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
Electrical Characteristics - DC
T
A
= 0 - 70 C; V
DD
= 2.5 V +/-200mV, V
DDQ
=2.5V 200mV; (unless otherwise stated)
SYM BOL
PARAMETERS
V
DD
MIN
TYP
MAX
UNITS
V
IK
I
I
= -18mA
2.3V
-1.2
I
OH
= -100A
2.3V-2.7
V
DD
-0.2
I
OH
= -16mA
2.3V
1.95
I
OL
= 100A
2.3-2.7V
0.2
I
OL
= 16mA
2.3V
0.35
I
I
All Inputs
V
I
= V
DD
or GND
2.7V
5
A
Standby (Static)
RESET# = GND
.01
A
Operating (Static)
V
I
= V
IH
(AC#) or V
IL
(AC),
RESET# = V
DD
TBD
mA
Dynamic operating
clock only
RESET = V
DD
, V
I
= V
IH(AC)
or V
IL (AC)
, CK and CK#
switching 50% duty cycle.
TBD
/clock MHz
Dynamic Operating
per each data input
RESET# = V
DD
, V
I
= V
IH(AC)
or VIL (AC), CK and CK#
switching 50% duty cycle.
One data input switching at
half clock frequency, 50%
duty cycle
TBD
A/ clock
MHz/data
r
OH
Output High
2.3-2.7V
7
20
r
OL
Output Low
2.3-2.7V
7
20
r
O(
)
[r
OH
-
r
OL
] each
separate bit
2.5V
4
Data Inputs
2.5
3.5
CK and CK#
2.5
3.5
Notes:
1 - Guaranteed by design, not 100% tested in production.
I
O
= 0
CONDITIONS
2.7V
2.5V
V
I
= V
REF
350Mv
V
ICR
= 1.25V, V
I(PP)
= 360mV
pF
I
OH
= 20mA
V
C
i
I
OL
= 20mA
I
O
= 20mA, T
A
= 25 C
V
OH
V
OL
I
DD
I
DDD
5
ICSSSTV16859
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
M IN
M AX
f
clo ck
Clock frequency
200
M Hz
t
PD
Clock to output time
TBD
ns
t
RST
Reset to outp ut time
5
ns
t
SL
Outpu t slew rate
1
4
V/ns
Setup time, fast slew rate
2, 4
0.75
ns
Setup time, slow slew rate
3 , 4
0.9
ns
Hold time, fast slew rate
2 , 4
0.75
ns
Hold time, slow slew rate
3 , 4
0.9
ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate=
1V/ns.
4 - CLK, CLK# signals input slew rates are=
=1V/ns.
SYM BOL
t
SU
T
h
Note s:
3 - For data signal input slew rate=
=0.5V/ns and < 1V/ns.
V
DD
= 2.5V 0.2V
UNITS
PARAM ETERS
Data before C K
, CK#
Data after CK
, CK#
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
M IN
TYP
M AX
fmax
200
M Hz
t
PD
C LK, CLK#
Q
1.1
2.8
ns
t
ph 1
C LK, CLK#
Q
5
ns
SYM BOL
V
DD
= 2.5V 0.2V
UNITS
From
(Input)
To
(Output)
PDF 
ZIP