Integrated
Circuit
Systems, Inc.
ICSSSTVA16857
0932A--05/12/04
Pin Configuration
DDR 14-Bit Registered Buffer
Truth Table
1
Block Diagram
Notes:
1.
H = High Signal Level
L = Low Signal Level
= Transition LOW-to-HIGH
= Transition HIGH -to LOW
X = Irrelevant
2.
Output level before the indicated
steady state input conditions were
established.
s
t
u
p
n
I
s
t
u
p
t
u
O
Q
#
T
E
S
E
R
K
L
C
#
K
L
C
D
Q
L
r
o
X
g
n
i
t
a
o
l
F
r
o
X
g
n
i
t
a
o
l
F
r
o
X
g
n
i
t
a
o
l
F
L
H
H
H
H
L
L
H
H
r
o
L
H
r
o
L
X
Q
0
)
2
(
48-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP
Recommended Applications:
DDR Memory Modules
Provides complete DDR DIMM logic solution with
ICS93V857 or ICS95V857
SSTL_2 compatible data registers
DDR400 recommended (backward compatible to
DDR200/266/333)
Product Features:
Exceeds "SSTVN16857" performance
Differential clock signal
Meets SSTL_2 signal data
Supports SSTL_2 class I & II specifications
Low-voltage operation
- V
DD
= 2.3V to 2.7V
48 pin TSSOP package
CLK
CLK#
38
39
48
35
34
D1
VREF
RESET#
To 13 Other Channels
Q1
1
CLK
R
D1
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK#
CLK
VDD
GND
VREF
RESET#
D8
D9
D10
D11
D12
VDD
GND
D13
D14
ICSSSTVA16857
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2
ICSSSTVA16857
0932A--05/12/04
General Description
Pin Configuration
R
E
B
M
U
N
N
I
P
E
M
A
N
N
I
P
E
P
Y
T
N
O
I
T
P
I
R
C
S
E
D
,
8
1
,
9
1
,
0
2
,
3
2
,
4
2
,
7
,
0
1
,
1
1
,
4
1
,
5
1
1
,
2
,
5
,
6
)
1
:
4
1
(
Q
T
U
P
T
U
O
t
u
p
t
u
o
a
t
a
D
,
2
2
,
3
1
,
8
,
3
6
4
,
6
3
,
7
2
D
N
G
R
W
P
d
n
u
o
r
G
1
2
,
6
1
,
2
1
,
9
,
4
Q
D
D
V
R
W
P
e
g
a
t
l
o
v
y
l
p
p
u
s
t
u
p
t
u
O
,
1
3
,
0
3
,
9
2
,
6
2
,
5
2
,
2
4
,
1
4
,
0
4
,
3
3
,
2
3
8
4
,
7
4
,
4
4
,
3
4
)
1
:
4
1
(
D
T
U
P
N
I
t
u
p
n
i
a
t
a
D
8
3
K
L
C
T
U
P
N
I
t
u
p
n
i
k
c
o
l
c
e
v
i
t
i
s
o
P
9
3
#
K
L
C
T
U
P
N
I
t
u
p
n
i
k
c
o
l
c
e
v
i
t
a
g
e
N
5
4
,
7
3
,
8
2
D
D
V
R
W
P
e
g
a
t
l
o
v
y
l
p
p
u
s
e
r
o
C
4
3
#
T
E
S
E
R
T
U
P
N
I
)
w
o
l
e
v
i
t
c
a
(
t
e
s
e
R
5
3
F
E
R
V
T
U
P
N
I
e
g
a
t
l
o
v
e
c
n
e
r
e
f
e
r
t
u
p
n
I
The 14-bit ICSSSTVA16857 is a universal bus driver designed for 2.3V to 2.7V V
DD
operation and SSTL_2 I/O levels,
except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge
of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an
LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTVA16857 supports low-power
standby operation. A logic level "Low" at RESET# assures that all internal registers and outputs (Q) are reset to the logic
"Low" state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET# must always
be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic
"Low" level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic "Low" level quickly relative to the time to disable the
differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level "Low" and the clock is stable during the "Low"-to-"High" transition of RESET# until the
input receivers are fully enabled, the design ensures that the outputs will remain at a logic "Low" level.
3
ICSSSTVA16857
0932A--05/12/04
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . 65C to +150C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V
Input Voltage
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.5 to V
DD
+0.5
Output Voltage
1,2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.5 to V
DDQ
+0.5
Input Clamp Current . . . . . . . . . . . . . . . . . . . . 50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . 50 mA
Continuous Output Current . . . . . . . . . . . . . . . 50 mA
V
DD
, V
DDQ
or GND Current/Pin . . . . . . . . . . . . 100 mA
Package Thermal Impedance
3
. . . . . . . . . . . . . . . .
55C/W
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Notes:
1. The input and output negative voltage
ratings may be excluded if the input
and output clamp ratings are observed.
2. This current will flow only when the
output is in the high state level
V
0
>V
DDQ
.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Recommended Operating Conditions - DDRI/DDR333 (PC1600, PC2100, PC2700)
PARAMETER
MIN
TYP
MAX
UNITS
V
DD
2.3
2.5
2.7
V
DDQ
2.3
2.5
2.7
V
REF
1.15
1.25
1.35
V
TT
V
REF
- 0.04
V
REF
V
REF
+ 0.04
V
I
Input Voltage
0
V
DDQ
V
IH (DC)
DC Input High Voltage
V
REF
+ 0.15
V
IH (AC)
AC Input High Voltage
V
REF
+ 0.31
V
IL (DC)
DC Input Low Voltage
V
REF
- 0.15
V
IL
(DC)
AC Input Low Voltage
V
REF
- 0.31
V
IH
Input High Voltage Level
1.7
V
IL
Input Low Voltage Level
0.7
V
ICR
Common mode Input Range
0.97
1.53
V
ID
Differential Input Voltage
0.36
V
IX
(V
DDQ
/2) - 0.2
(V
DDQ
/2) + 0.2
I
OH
-16
I
OL
16
T
A
0
70
C
1
Guaranteed by design, not 100% tested in production.
Operating Free-Air Temperature
RESET#
CLK, CLK#
V
Termination Voltage
Cross Point Voltage of Differential Clock
Pair
High-Level Output Current
Low-Level Output Current
Data Inputs
mA
DESCRIPTION
Supply Voltage
I/O Supply Voltage
Reference Voltage
4
ICSSSTVA16857
0932A--05/12/04
Recommended Operating Conditions - DDRI-400 (PC3200)
PARAMETER
MIN
TYP
MAX
UNITS
V
DD
2.5
2.6
2.7
V
DDQ
2.5
2.6
2.7
V
REF
1.25
1.3
1.35
V
TT
V
REF
- 0.04
V
REF
V
REF
+ 0.04
V
I
Input Voltage
0
V
DDQ
V
IH (DC)
DC Input High Voltage
V
REF
+ 0.15
V
IH (AC)
AC Input High Voltage
V
REF
+ 0.31
V
IL (DC)
DC Input Low Voltage
V
REF
- 0.15
V
IL
(DC)
AC Input Low Voltage
V
REF
- 0.31
V
IH
Input High Voltage Level
1.7
V
IL
Input Low Voltage Level
0.7
V
ICR
Common mode Input Range
0.97
1.53
V
ID
Differential Input Voltage
0.36
V
IX
(V
DDQ
/2) - 0.2
(V
DDQ
/2) + 0.2
I
OH
-16
I
OL
16
T
A
0
70
C
1
Guaranteed by design, not 100% tested in production.
Operating Free-Air Temperature
RESET#
CLK, CLK#
V
Termination Voltage
Cross Point Voltage of Differential Clock
Pair
High-Level Output Current
Low-Level Output Current
Data Inputs
mA
DESCRIPTION
Supply Voltage
I/O Supply Voltage
Reference Voltage
5
ICSSSTVA16857
0932A--05/12/04
DC Electrical Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700)
T
A
= 0 - 70C; V
DD
= 2.5 +/-0.2V, V
DDQ
=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
PARAMETERS
V
DDQ
MIN
TYP
MAX
UNITS
V
IK
I
I
= -18mA
2.3V
-1.2
I
OH
= -100A
2.3V-2.7V
V
DDQ
-
0.2
I
OH
= -8mA
2.3V
1.95
I
OL
= 100A
2.3V-2.7V
0.2
I
OL
= 8mA
2.3V
0.35
I
I
All Inputs
V
I
= V
DD
or GND
2.7V
5
A
Standby (Static)
RESET# = GND
0.01
A
Operating (Static)
V
I
= V
IH(AC)
or V
IL(AC)
,
RESET# = V
DD
25
mA
Dynamic operating
(clock only)
RESET# = V
DD
,
V
I
= V
IH(AC)
or V
IL(AC)
,
CLK and CLK# switching
50% duty cycle.
30
/clock
MHz
Dynamic Operating
(per each data input)
RESET# = V
DD
,
V
I
= V
IH(AC)
or V
IL (AC)
,
CLK and CLK# switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
10
A/ clock
MHz/data
r
OH
Output High
2.3V-2.7V
7
13.5
20
r
OL
Output Low
2.3V-2.7V
7
13
20
r
O(D)
[r
OH
-
r
OL
] each
separate bit
2.5V
4
Data Inputs
2.5
3.5
CLK and CLK#
2.5
3.5
Notes:
1 - Guaranteed by design, not 100% tested in production.
I
O
= 0
CONDITIONS
2.7V
2.5V
V
I
= V
REF
350mV
V
ICR
= 1.25V, V
I(PP)
= 360mV
pF
I
OH
= -16mA
V
C
i
I
OL
= 16mA
I
O
= 20mA, T
A
= 25 C
V
OH
V
OL
I
DD
I
DDD
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