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Электронный компонент: ICSSSTVA16859BGLF-T

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Integrated
Circuit
Systems, Inc.
ICSSSTVA16859B
1050A--01/07/05
Recommended Applications:
 DDR Memory Modules:
- DDRI (PC1600, PC2100)
- DDR333 (PC2700)
- DDRI-400 (PC3200)
Provides complete DDR DIMM solution with
ICS93V857 or ICS95V857
SSTL_2 compatible data registers
Product Features:
 Differential clock signals
Meets SSTL_2 signal data
Supports SSTL_2 class I specifications on outputs
Low-voltage operation
- V
DD
= 2.3V to 2.7V
Available in 64 pin TSSOP and 56 pin MLF packages
Exceeds SSTVN16859 performance
DDR 13-Bit to 26-Bit Registered Buffer
Truth Table
1
Block Diagram
Notes:
1.
H = "High" Signal Level
L = "Low" Signal Level
= Transition "Low"-to-"High"
= Transition "High"-to-"Low"
X = Don't Care
2.
Output level before the indicated steady state
input conditions were established.
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Q
0
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2
(
CLK
CLK#
D1
VREF
RESET#
To 12 Other Channels
Q1A
Q1B
CLK
R
D1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
Q7B
Q6B
GND
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
VDDQ
GND
D13
D12
VDD
VDDQ
GND
D11
D10
D9
GND
D8
D7
RESET#
GND
CLK#
CLK
VDDQ
VDD
VREF
D6
GND
D5
D4
D3
GND
VDDQ
VDD
D2
D1
GND
VDDQ
IC
SSSTVA
16859B
Pin Configurations
64-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
1
14
15
28
29
43
42
56
D10
D9
D8
D7
RESET#
GND
CLK#
CLK
VDDQ
VDD
VREF
D6
D5
D4
Q8A
V
DDQ
Q9A
Q10A
Q11A
Q12A
Q13A
V
DDQ
GND
D13
D12
VD
D
V
DDQ
D11
Q7B
Q6B
V
DDQ
Q5B
Q4B
Q3B
Q2B
Q1B
V
DDQ
D1
D2
VD
D
V
DDQ
D3
ICSSSTVA16859B
56-Pin VFQFN (MLF2)
ICSSSTVA16859B
1050A--01/07/05
General Description
Pin Configuration (64-Pin TSSOP)
The 13-bit-to-26-bit ICSSSTVA16859B is a universal bus driver designed for 2.3V to 2.7V V
DD
operation and SSTL_2
I/O levels, except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive
edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#,
an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTVA16859B supports low-
power standby operation. A logic level "Low" at RESET# assures that all internal registers and outputs (Q) are reset
to the logic "Low" state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that
RESET# must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during
power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held
at a logic "Low" level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic "Low" level quickly relative to the time to disable
the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level "Low" and the clock is stable during the "Low"-to-"High" transition of RESET# until
the input receivers are fully enabled, the design ensures that the outputs will remain at a logic "Low" level.
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Pin Configuration (56-Pin MLF2)
ICSSSTVA16859B
1050A--01/07/05
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . 65C to +150C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V
Input Voltage
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.5 to V
DD
+0.5
Output Voltage
1,2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.5 to V
DDQ
+0.5
Input Clamp Current . . . . . . . . . . . . . . . . . . . . 50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . 50 mA
Continuous Output Current . . . . . . . . . . . . . . . 50 mA
V
DD
, V
DDQ
or GND Current/Pin . . . . . . . . . . . 100 mA
Package Thermal Impedance
3
. . . . . . . . . . . . . . .
55C/W
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Notes:
1. The input and output negative voltage
ratings may be excluded if the input
and output clamp ratings are observed.
2. This current will flow only when the
output is in the high state level
V
0
>V
DDQ
.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Recommended Operating Conditions - DDRI/DDR333 (PC1600, PC2100, PC2700)
PARAMETER
MIN
TYP
MAX
UNITS
V
DD
2.3
2.5
2.7
V
DDQ
2.3
2.5
2.7
V
REF
1.15
1.25
1.35
V
TT
V
REF
- 0.04
V
REF
V
REF
+ 0.04
V
I
Input Voltage
0
V
DDQ
V
IH (DC)
DC Input High Voltage
V
REF
+ 0.15
V
IH (AC)
AC Input High Voltage
V
REF
+ 0.31
V
IL (DC)
DC Input Low Voltage
V
REF
- 0.15
V
IL
(DC)
AC Input Low Voltage
V
REF
- 0.31
V
IH
Input High Voltage Level
1.7
V
IL
Input Low Voltage Level
0.7
V
ICR
Common mode Input Range
0.97
1.53
V
ID
Differential Input Voltage
0.36
V
IX
(V
DDQ
/2) - 0.2
(V
DDQ
/2) + 0.2
I
OH
-16
I
OL
16
T
A
0
70
C
1
Guaranteed by design, not 100% tested in production.
Operating Free-Air Temperature
RESET#
CLK, CLK#
V
Termination Voltage
Cross Point Voltage of Differential Clock
Pair
High-Level Output Current
Low-Level Output Current
Data Inputs
mA
DESCRIPTION
Supply Voltage
I/O Supply Voltage
Reference Voltage
ICSSSTVA16859B
1050A--01/07/05
Recommended Operating Conditions - DDRI-400 (PC3200)
PARAMETER
MIN
TYP
MAX
UNITS
V
DD
2.5
2.6
2.7
V
DDQ
2.5
2.6
2.7
V
REF
1.25
1.3
1.35
V
TT
V
REF
- 0.04
V
REF
V
REF
+ 0.04
V
I
Input Voltage
0
V
DDQ
V
IH (DC)
DC Input High Voltage
V
REF
+ 0.15
V
IH (AC)
AC Input High Voltage
V
REF
+ 0.31
V
IL (DC)
DC Input Low Voltage
V
REF
- 0.15
V
IL
(DC)
AC Input Low Voltage
V
REF
- 0.31
V
IH
Input High Voltage Level
1.7
V
IL
Input Low Voltage Level
0.7
V
ICR
Common mode Input Range
0.97
1.53
V
ID
Differential Input Voltage
0.36
V
IX
(V
DDQ
/2) - 0.2
(V
DDQ
/2) + 0.2
I
OH
-16
I
OL
16
T
A
0
70
C
1
Guaranteed by design, not 100% tested in production.
Operating Free-Air Temperature
RESET#
CLK, CLK#
V
Termination Voltage
Cross Point Voltage of Differential Clock
Pair
High-Level Output Current
Low-Level Output Current
Data Inputs
mA
DESCRIPTION
Supply Voltage
I/O Supply Voltage
Reference Voltage
ICSSSTVA16859B
1050A--01/07/05
DC Electrical Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700)
T
A
= 0 - 70C; V
DD
= 2.5 +/-0.2V, V
DDQ
=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
PARAMETERS
V
DDQ
MIN
TYP
MAX
UNITS
V
IK
I
I
= -18mA
2.3V
-1.2
I
OH
= -100A
2.3V-2.7V
V
DDQ
-
0.2
I
OH
= -8mA
2.3V
1.95
I
OL
= 100A
2.3V-2.7V
0.2
I
OL
= 8mA
2.3V
0.35
I
I
All Inputs
V
I
= V
DD
or GND
2.7V
5
A
Standby (Static)
RESET# = GND
0.01
A
Operating (Static)
V
I
= V
IH(AC)
or V
IL(AC)
,
RESET# = V
DD
TBD
mA
Dynamic operating
(clock only)
RESET# = V
DD
, V
I
= V
IH(AC)
or V
IL(AC)
, CLK
and CLK# switching 50%
duty cycle.
TBD
/clock MHz
Dynamic Operating
(per each data input)
RESET# = V
DD
, V
I
= V
IH(AC)
or V
IL (AC)
, CLK
and CLK# switching 50%
duty cycle. One data input
switching at half clock
frequency, 50% duty cycle
TBD
A/ clock
MHz/data
r
OH
Output High
2.3V-2.7V
7
13.5
20
r
OL
Output Low
2.3V-2.7V
7
13
20
r
O(D)
[r
OH
-
r
OL
] each
separate bit
2.5V
4
Data Inputs
2.5
3.5
CLK and CLK#
2.5
3.5
Notes:
1 - Guaranteed by design, not 100% tested in production.
I
O
= 0
CONDITIONS
2.7V
2.5V
V
I
= V
REF
350mV
V
ICR
= 1.25V, V
I(PP)
= 360mV
pF
I
OH
= -16mA
V
C
i
I
OL
= 16mA
I
O
= 20mA, T
A
= 25 C
V
OH
V
OL
I
DD
I
DDD