Integrated
Circuit
Systems, Inc.
ICS951411
0891E--03/07/05
Pin Configuration
Recommended Application:
ATI RS400 systems using Intel P4
TM
processors
Output Features:
6 - Pairs of SRC/PCI-Express clocks
2 - Pairs of ATIG (SRC/PCI Express*) clocks
3 - Pairs of Intel P4 clocks
3 - 14.318 MHz REF clocks
1 - 48MHz USB clock
1 - 33 MHz PCI clock seed
Key Specifications:
CPU outputs cycle-cycle jitter < 85ps
SRC output cycle-cycle jitter <125ps
PCI outputs cycle-cycle jitter < 250ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
System Clock Chip for ATI RS400 P4
TM
-based Systems
Features/Benefits:
2- Programmable Clock Request pins for SRC clocks
Supports CK410 or CK409 frequency table mapping
Spread Spectrum for EMI reduction
Outputs may be disabled via SMBus
External crystal load capacitors for maximum
frequency accuracy
56-pin SSOP & TSSOP
*Other names and brands may be claimed as the property of others.
Functionality - (CK410# = 0)
FS_C
1
FS_B
1
FS_A
1
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
U
SB
MHz
0
266.66 100.00 33.33
14.318 48.000
1
133.33 100.00 33.33
14.318 48.000
0
200.00 100.00 33.33
14.318 48.000
1
166.66 100.00 33.33
14.318 48.000
0
333.33 100.00 33.33
14.318 48.000
1
100.00 100.00 33.33
14.318 48.000
0
400.00 100.00 33.33
14.318 48.000
1
14.318 48.000
Functionality - (CK410# = 1)
FS_C
1
Byte6
bit5
FS_B
1
FS_A
1
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
U
SB
MHz
0
0
100.00 100.00 33.33
14.318 48.000
1
0
200.00 100.00 33.33
14.318 48.000
0
1
133.33 100.00 33.33
14.318 48.000
1
1
166.67 100.00 33.33
14.318 48.000
0
0
200.00 100.00 33.33
14.318 48.000
1
0
400.00 100.00 33.33
14.318 48.000
0
1
266.67 100.00 33.33
14.318 48.000
1
1
333.33 100.00 33.33
14.318 48.000
1. FS_C, FS_B and FS_A are low-threshold inputs. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
RESERVED
1
0
0
0
1
1
0
1
X1 1
56 VDDREF
X2 2
55 GND
VDD48 3
54 **FS_A/REF0
USB_48MHz 4
53 **FS_B/REF1
GND 5
52 **TEST_SEL/REF2
VTT_PWRGD#/PD 6
51 VDDPCI
SCLK 7
50 **CK410#/PCICLK0
SDATA 8
49 GNDPCI
**FS_C 9
48 *CPU_STOP#
**CLKREQA# 10
47 CPUCLKT0
**CLKREQB# 11
46 CPUCLKC0
SRCCLKT7 12
45 VDDCPU
SRCCLKC7 13
44 GNDCPU
VDDSRC 14
43 CPUCLKT1
GNDSRC 15
42 CPUCLKC1
SRCCLKT6 16
41 CPUCLKT2_ITP
SRCCLKC6 17
40 CPUCLKC2_ITP
SRCCLKT5 18
39 VDDA
SRCCLKC5 19
38 GNDA
GNDSRC 20
37 IREF
VDDSRC 21
36 GNDSRC
SRCCLKT4 22
35 VDDSRC
SRCCLKC4 23
34 SRCCLKT0
SRCCLKT3 24
33 SRCCLKC0
SRCCLKC3 25
32 VDDATI
GNDSRC 26
31 GNDATI
ATIGCLKT1 27
30 ATIGCLKT0
ATIGCLKC1 28
29 ATIGCLKC0
Note: Pins preceeded by '**' have a 120 Kohm Internal Pull Down resistor
Pins preceeded by '*' have a 120 Kohm Internal Pull Up resistor
IC
S9
514
11
2
Integrated
Circuit
Systems, Inc.
ICS951411
0891E--03/07/05
Pin Description
PIN #
PIN NAME
PIN
TYPE
DESCRIPTION
1
X1
IN
Crystal input, Nominally 14.318MHz.
2
X2
OUT Crystal output, Nominally 14.318MHz
3
VDD48
PWR Power pin for the 48MHz output.3.3V
4
USB_48MHz
OUT 48.00MHz USB clock
5
GND
PWR Ground pin.
6
VTT_PWRGD#/PD
IN
Vtt_PwrGd# is an active low input used to determine when latched inputs are
ready to be sampled. PD is an asynchronous active high input pin used to put
the device into a low power state. The internal clocks, PLLs and the crystal
oscillator are stopped.
7
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
8
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
9
**FS_C
IN
Frequency select latch input pin
10
**CLKREQA#
IN
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
11
**CLKREQB#
IN
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
12
SRCCLKT7
OUT True clock of differential SRC clock pair.
13
SRCCLKC7
OUT Complement clock of differential SRC clock pair.
14
VDDSRC
PWR Supply for SRC clocks, 3.3V nominal
15
GNDSRC
PWR Ground pin for the SRC outputs
16
SRCCLKT6
OUT True clock of differential SRC clock pair.
17
SRCCLKC6
OUT Complement clock of differential SRC clock pair.
18
SRCCLKT5
OUT True clock of differential SRC clock pair.
19
SRCCLKC5
OUT Complement clock of differential SRC clock pair.
20
GNDSRC
PWR Ground pin for the SRC outputs
21
VDDSRC
PWR Supply for SRC clocks, 3.3V nominal
22
SRCCLKT4
OUT True clock of differential SRC clock pair.
23
SRCCLKC4
OUT Complement clock of differential SRC clock pair.
24
SRCCLKT3
OUT True clock of differential SRC clock pair.
25
SRCCLKC3
OUT Complement clock of differential SRC clock pair.
26
GNDSRC
PWR Ground pin for the SRC outputs
27
ATIGCLKT1
OUT True clock of differential SRC clock pair.
28
ATIGCLKC1
OUT Complementary clock of differential SRC clock pair.
3
Integrated
Circuit
Systems, Inc.
ICS951411
0891E--03/07/05
Pin Description (Continued)
PIN #
PIN NAME
PIN
TYPE
DESCRIPTION
29
ATIGCLKC0
OUT Complementary clock of differential SRC clock pair.
30
ATIGCLKT0
OUT True clock of differential SRC clock pair.
31
GNDATI
PWR Ground for ATI Gclocks, nominal 3.3V
32
VDDATI
PWR Power supply ATI Gclocks, nominal 3.3V
33
SRCCLKC0
OUT Complement clock of differential SRC clock pair.
34
SRCCLKT0
OUT True clock of differential SRC clock pair.
35
VDDSRC
PWR Supply for SRC clocks, 3.3V nominal
36
GNDSRC
PWR Ground pin for the SRC outputs
37
IREF
OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
38
GNDA
PWR Ground pin for the PLL core.
39
VDDA
PWR 3.3V power for the PLL core.
40
CPUCLKC2_ITP
OUT
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
41
CPUCLKT2_ITP
OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
42
CPUCLKC1
OUT
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
43
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
44
GNDCPU
PWR Ground pin for the CPU outputs
45
VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
46
CPUCLKC0
OUT
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
47
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
48
*CPU_STOP#
IN
Stops all CPUCLK, except those set to be free running clocks
49
GNDPCI
PWR Ground pin for the PCI outputs
50
**CK410#/PCICLK0
I/O
FS Table select latch input pin / 3.3V PCI clock output.
0 = CK410 FS Table, 1 = CK409 FS Table
51
VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
52
**TEST_SEL/REF2
I/O
TEST_SEL: latched input to select TEST MODE / 14.318 MHz reference clock.
1 = All outputs are CK410 REF/N test mode
0 = All outputs behave normally.
53
**FS_B/REF1
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
54
**FS_A/REF0
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
55
GND
PWR Ground pin.
56
VDDREF
PWR Ref, XTAL power supply, nominal 3.3V
4
Integrated
Circuit
Systems, Inc.
ICS951411
0891E--03/07/05
ICS951411 provides a single-chip clocking solution for the ATI RS400-based systems using the latest Intel P4 processors.
ICS951411 is driven with a 14.318MHz crystal. It generates CPU outputs up to 400MHz and also provides highly accurate
SRC clocks for PCI Express support. Two Clock Request pins are provided for Express-Card
TM
support.
General Description
Block Diagram
Power Groups
MAIN PLL
PCICLK0
CONTROL
LOGIC
XTAL
OSC.
CPUCLK(2:0)
FIXED PLL
USB_48MHz
DIVIDER
DIVIDERS
REF(2:0)
SRCCLK(7:3,0)
CLKREQA#
SDATA
SCLK
CLKREQB#
X1
X2
IREF
FS(C:A)
CPU_STOP#
VTT_PWRGD#/PD
ATIGCLK(1:0)
CK410#
VDD
GND
56
55
Xtal, REF
51
49
PCICLK output
45
44
CPUCLK Outputs
14, 21, 35 15, 20, 26, 36
SRCCLK outputs
32
31
ATIGCLK outputs
39
38
Analog, CPU PLL
3
5
USB_48MHz output
Pin Number
Description
5
Integrated
Circuit
Systems, Inc.
ICS951411
0891E--03/07/05
General SMBus serial interface information for the ICS951411
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byt
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byt
e
ACK
ACK
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