INDUSTRIAL TEMPERATURE RANGE

IDT5T905
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER

FEBRUARY 2003

IDT5T905

PRELIMINARY

INDUSTRIAL TEMPERATURE RANGE

2.5V SINGLE DATA RATE

1:5 CLOCK BUFFER
TERABUFFERTM

DESCRIPTION:

The IDT5T905 2.5V single data rate (SDR) clock buffer is a user-selectable

single-ended or differential input to five single-ended outputs buffer built on
advanced metal CMOS technology. The SDR clock buffer fanout from a single
or differential input to five single-ended outputs reduces the loading on the
preceding driver and provides an efficient clock distribution network. The
IDT5T905 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V
LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL,
1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input
signals that may be hard-wired to appropriate high-mid-low levels. Multiple
power and grounds reduce noise.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

DSC-5942/24

FEATURES:

· Guaranteed Low Skew < 25ps (max)
· Very low duty cycle distortion
· High speed propagation delay < 2.5ns. (max)
· Up to 250MHz operation
· Very low CMOS power levels
· 1.5V V

DDQ

for HSTL interface

· Hot insertable and over-voltage tolerant inputs
· 3-level inputs for selectable interface
· Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input

interface

· Selectable differential or single-ended inputs and five single-

ended outputs

· 2.5V V

· Available in TSSOP package

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS:

· Clock and signal distribution

TxS

RxS

A/V

REF

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

INDUSTRIAL TEMPERATURE RANGE

IDT5T905
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER

TSSOP

TOP VIEW

PIN CONFIGURATION

GND

DDQ

GND

DDQ

GND

A/V

REF

DDQ

GND

DDQ

RxS

TxS

Symbol

Description

Max

Unit

Power Supply Voltage

(2)

0.5 to +3.6

DDQ

Output Power Supply

(2)

0.5 to +3.6

Input Voltage

0.5 to +3.6

Output Voltage

(3)

0.5 to V

DDQ

+0.5

REF

Reference Voltage

(3)

0.5 to +3.6

STG

Storage Temperature

65 to +165

°C

Junction Temperature

150

°C

ABSOLUTE MAXIMUM RATINGS

(1)

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. V

DDQ

and V

internally operate independently. No power sequencing requirements

need to be met.

3. Not to exceed 3.6V.

Symbol

Parameter

Min

Typ.

Max.

Unit

Input Capacitance

3.5

CAPACITANCE

(1,2)

= +25°C, F = 1.0MHz)

NOTES:
1. This parameter is measured at characterization but not tested.
2. Capacitance applies to all inputs except RxS and TxS.

Symbol

Description

Min.

Typ.

Max.

Unit

Ambient Operating Temperature

+25

+85

°C

(1)

Internal Power Supply Voltage

2.4

2.5

2.6

HSTL Output Power Supply Voltage

1.4

1.5

1.6

DDQ

(1)

Extended HSTL and 1.8V LVTTL Output Power Supply Voltage

1.65

1.8

1.95

2.5V LVTTL Output Power Supply Voltage

Termination Voltage

DDQ

/ 2

RECOMMENDED OPERATING RANGE

NOTE:
1. All power supplies should operate in tandem. If V

or V

DDQ

is at maximum, then V

DDQ

or V

(respectively) should be at maximum, and vice-versa.

INDUSTRIAL TEMPERATURE RANGE

IDT5T905
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER

PIN DESCRIPTION

Symbol

I/O

Type

Description

Adjustable

(1)

Clock input. A is the "true" side of the differential clock input. If operating in single-ended mode, A is the clock input.

A/V

REF

Adjustable

(1)

Complementary clock input. A/V

REF

is the "complementary" side of A if the input is in differential mode. If operating in single-ended

mode, A/V

REF

is connected to GND. For single-ended operation in differential mode, A/V

REF

should be set to the desired toggle

voltage for A:

2.5V LVTTL

REF

= 1250mV

1.8V LVTTL, eHSTL

REF

= 900mV

HSTL

REF

= 750mV

LVEPECL

REF

= 1082mV

LVTTL

(5)

Gate control for Qn outputs. When G is LOW, these outputs are enabled. When G is HIGH, these outputs are asynchronously
disabled to the level designated by GL

(4)

LVTTL

(5)

Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW.

Adjustable

(2)

Clock outputs

RxS

3 Level

(3)

Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) clock input or differential (LOW) clock input

TxS

3 Level

(3)

Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL (LOW) compatible. Used in
conjunction with V

DDQ

to set the interface levels.

PWR

Power supply for the device core and inputs

DDQ

PWR

Power supply for the device outputs. When utilizing 2.5V LVTTL outputs, V

DDQ

should be connected to V

GND

PWR

Power supply return for all power

NOTES:
1. Inputs are capable of translating the following interface standards. User can select between:

Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels

2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate V

DDQ

voltage.

3. 3 level inputs are static inputs and must be tied to V

or GND or left floating. These inputs are not hot-insertable or over-voltage tolerant.

4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt

pulses or be able to tolerate them in down stream circuitry.

5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.

INDUSTRIAL TEMPERATURE RANGE

IDT5T905
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER

INPUT/OUTPUT SELECTION

(1)

Input

Output

2.5V LVTTL SE

2.5V LVTTL

1.8V LVTTL SE

2.5V LVTTL DSE
1.8V LVTTL DSE

LVEPECL DSE

eHSTL DSE

HSTL DSE

2.5V LVTTL DIF
1.8V LVTTL DIF

LVEPECL DIF

eHSTL DIF

HSTL DIF

2.5V LVTTL SE

1.8V LVTTL

1.8V LVTTL SE

2.5V LVTTL DSE
1.8V LVTTL DSE

LVEPECL DSE

eHSTL DSE

HSTL DSE

2.5V LVTTL DIF
1.8V LVTTL DIF

LVEPECL DIF

eHSTL DIF

HSTL DIF

Input

Output

2.5V LVTTL SE

eHSTL

1.8V LVTTL SE

2.5V LVTTL DSE
1.8V LVTTL DSE

LVEPECL DSE

eHSTL DSE

HSTL DSE

2.5V LVTTL DIF
1.8V LVTTL DIF

LVEPECL DIF

eHSTL DIF

HSTL DIF

2.5V LVTTL SE

HSTL

1.8V LVTTL SE

2.5V LVTTL DSE
1.8V LVTTL DSE

LVEPECL DSE

eHSTL DSE

HSTL DSE

2.5V LVTTL DIF
1.8V LVTTL DIF

LVEPECL DIF

eHSTL DIF

HSTL DIF

NOTE:
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require the

A/V

REF

pin to be connected to GND. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring a V

REF

. Differential (DIF) inputs are used only in

differential mode.

NOTE:
1. These inputs are normally wired to V

, GND, or left floating. Internal termination resistors bias unconnected unputs to V

/2.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Symbol

Parameter

Test Conditions

Min.

Max

Unit

IHH

Input HIGH Voltage Level

(1)

3-Level Inputs Only

0.4

IMM

Input MID Voltage Level

(1)

3-Level Inputs Only

/2 0.2 V

/2 + 0.2

ILL

Input LOW Voltage Level

(1)

3-Level Inputs Only

0.4

= V

HIGH Level

200

3-Level Input DC Current (RxS, TxS)

= V

MID Level

+50

µA

= GND

LOW Level

200

INDUSTRIAL TEMPERATURE RANGE

IDT5T905
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER

POWER SUPPLY CHARACTERISTICS FOR HSTL OUTPUTS

(1)

Symbol

Parameter

Test Conditions

(2)

Typ.

Max

Unit

DDQ

Quiescent V

Power Supply Current

DDQ

= Max., Reference Clock = LOW

(3)

Outputs enabled, All outputs unloaded

DDQQ

Quiescent V

DDQ

Power Supply Current

DDQ

= Max., Reference Clock = LOW

(3)

0.1

0.3

Outputs enabled, All outputs unloaded

DDD

Dynamic V

Power Supply

= Max., V

DDQ

= Max., C

= 0pF

µA/MHz

Current per Output

DDDQ

Dynamic V

DDQ

Power Supply

= Max., V

DDQ

= Max., C

= 0pF

µA/MHz

Current per Output

TOT

Total Power V

Supply Current

DDQ

= 1.5V, F

REFERENCE

CLOCK

= 100MHz, C

= 15pF

DDQ

= 1.5V, F

REFERENCE

CLOCK

= 250MHz, C

= 15pF

TOTQ

Total Power V

DDQ

Supply Current

DDQ

= 1.5V, F

REFERENCE

CLOCK

= 100MHz, C

= 15pF

DDQ

= 1.5V, F

REFERENCE

CLOCK

= 250MHz, C

= 15pF

NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR HSTL

(1)

Symbol

Parameter

Test Conditions

Min.

Typ.

(7)

Max

Unit

Input Characteristics

Input HIGH Current

(9)

= 2.6V

= V

DDQ

/GND

±5

µA

Input LOW Current

(9)

= 2.6V

= GND/V

DDQ

±5

Clamp Diode Voltage

= 2.4V, I

= -18mA

- 0.7

- 1.2

DC Input Voltage

- 0.3

+3.6

DIF

DC Differential Voltage

(2,8)

0.2

DC Common Mode Input Voltage

(3,8)

680

750

900

DC Input HIGH

(4,5,8)

REF

+ 100

DC Input LOW

(4,6,8)

REF

- 100

REF

Single-Ended Reference Voltage

(4,8)

750

Output Characteristics

Output HIGH Voltage

= -8mA

DDQ

- 0.4

= -100

µA

DDQ

- 0.1

Output LOW Voltage

= 8mA

0.4

= 100

µA

0.1

NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. V

DIF

specifies the minimum input differential voltage (V

- V

) required for switching where V

is the "true" input level and V

is the "complement" input level. Differential mode

only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.

3. V

specifies the maximum allowable range of (V

+ V

) /2. Differential mode only.

4. For single-ended operation, in differential mode, A/V

REF

is tied to the DC voltage V

REF

5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at V

= 2.5V, V

DDQ

= 1.5V, +25°C ambient.

8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be

referenced.

9. For differential mode (RxS = LOW), A and A/V

REF

must be at the opposite rail.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 5T905

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 5T905