INDUSTRIAL TEMPERATURE RANGE

IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

FEBRUARY 2002

2002 Integrated Device Technology, Inc.

DSC 5851/4

INDUSTRIAL TEMPERATURE RANGE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

· Ref input is 5V tolerant
· 4 pairs of programmable skew outputs
· Low skew: 185ps same pair, 250ps all outputs
· Selectable positive or negative edge synchronization:

Excellent for DSP applications

· Synchronous output enable
· Input frequency: 2MHz to 200MHz
· Output frequency: 6MHz to 200MHz
· 3-level inputs for skew and PLL range control
· 3-level inputs for feedback divide selection multiply / divide

ratios of (1-6, 8, 10, 12) / (2, 4)

· PLL bypass for DC testing
· External feedback, internal loop filter
· 12mA balanced drive outputs
· Low Jitter: <100ps cycle-to-cycle
· Power-down mode
· Lock indicator
· Available in TQFP package

FUNCTIONAL BLOCK DIAGRAM

P E

LO CK

P LL

sOE

RE F

/ N

S kew

S elect

S kew

S elect

S kew

S elect

S kew

S elect

1F1:0

2F1:0

DS 1:0

3F1:0

4F1:0

P D

TE S T

IDT5V995

PRELIMINARY

3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCKTM II

DESCRIPTION:

The IDT5V995 is a high fanout 3.3V PLL based clock driver intended for

high performance computing and data-communications applications. A key
feature of the programmable skew is the ability of outputs to lead or lag the
REF input signal. The IDT5V995 has eight programmable skew outputs in
four banks of 2. Skew is controlled by 3-level input signals that may be hard-
wired to appropriate HIGH-MID-LOW levels.

The feedback input allows divide-by-functionality from 1 to 12 through the

use of the DS[1:0] inputs. This provides the user with frequency
multiplication from 1 to 12 without using divided outputs for feedback.

When the

sOE pin is held low, all the outputs are synchronously enabled.

However, if

sOE is held high, all the outputs except 2Q0 and 2Q1 are

synchronously disabled. The LOCK output asserts to indicate when Phase
Lock has been achieved.

Furthermore, when PE is held high, all the outputs are synchronized with

the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF. The IDT5V995 has
LVTTL outputs with 12mA balanced drive outputs.

INDUSTRIAL TEMPERATURE RANGE

IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

PIN CONFIGURATION

NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Description

Max

Unit

DDQ

, V

Supply Voltage to Ground

0.5 to +4.6

DC Input Voltage

0.5 to V

+0.5

REF Input Voltage

0.5 to +5.5

Maximum Power

= 85°C

0.7

Dissipation

= 55°C

1.1

STG

Storage Temperature Range

65 to +150

° C

NOTE:
1. Capacitance applies to all inputs except TEST, FS, nF

[1:0]

, and DS

[1:0]

CAPACITANCE

= +25°C, f = 1MHz, V

= 0V)

Parameter

Description

Typ.

Max.

Unit

Input Capacitance

sOE

DD Q

G N D

DD Q

G N D

1 5

2 0

3 4

3 5

4 1

4 2

DD Q

G N D

D S

DD Q

G N D

LO C K

GND

TQFP

TOP VIEW

NOTE:
1. When TEST = MID and

sOE = HIGH, PLL remains active

with nF[

1:0

] = LL functioning as an output disable control for individual output banks. Skew selections remain in

effect unless nF[

1:0

] = LL.

PIN DESCRIPTION

Pin Name

Type

Description

REF

I N

Reference Clock Input

I N

Feedback Input

TEST

(1)

I N

When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary

Table) remain in effect. Set LOW for normal operation.

sOE

(1)

I N

Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q

and 2Q

) in a LOW state (for PE = H) - 2Q

and 2Q

may

be used as the feedback signal to maintain phase lock. When TEST is held at MID level and

sOE is HIGH, the nF[

1:0

] pins act as output

disable controls for individual banks when nF[

1:0

] = LL. Set

sOE LOW for normal operation (has internal pull-down).

I N

Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference

clock (has internal pull-up).

[1:0]

I N

3-level inputs for selecting 1 of 9 skew taps or frequency functions

I N

Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.)

[1:0]

OUT

Four banks of two outputs with programmable skew

[1:0]

I N

3-level inputs for feedback divider selection

I N

Power down control. Shuts off entire chip when LOW (has internal pull-up).

LOCK

OUT

PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the

inputs.

DDQ

PWR

Power supply for output buffers

PWR

Power supply for phase locked loop, lock output, and other internal circuitry

GND

PWR

Ground

INDUSTRIAL TEMPERATURE RANGE

IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

Output skew with respect to the REF input is adjustable to compensate

for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit (t

) which ranges

from 625ps to 1.3ns (see Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF

1:0

control pins. In order

to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF

1:0

control pins.

PROGRAMMABLE SKEW

EXTERNAL FEEDBACK

By providing external feedback, the IDT5V995 gives users flexibility

with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.

NOTES:

1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q

1:0

, 2Q

1:0

, and the

higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be F

NOM

when the output connected to FB is undivided

and DS[

1:0

] = MM. The frequency of the REF and FB inputs will be F

NOM

/2 or F

NOM

/4 when the part is configured for frequency multiplication by using a divided output as the

FB input and setting DS[

1:0

] = MM. Using the DS[

1:0

] inputs allows a different method for frequency multiplication (see Divide Selection Table).

3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example

if a 4t

skewed output is used for feedback, all other outputs will be skewed 4t

in addition to whatever skew value is programmed for those outputs. `Max adjustment' range

applies to output pairs 3 and 4 where ± 6t

skew adjustment is possible and at the lowest F

NOM

value.

An internal loop filter moderates the response of the VCO to the

phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.

FS = LOW

FS = MID

FS = HIGH

Comments

Timing Unit Calculation (t

)

1/(32 x F

NOM

)

1/(16 x F

NOM

)

1/(8 x F

NOM

)

VCO Frequency Range (F

NOM

)

(1,2)

24 to 50MHz

48 to 100MHz

96 to 200MHz

Skew Adjustment Range

(3)

Max Adjustment:

±7.8125ns

±67.5°

±135°

±270°

Phase Degrees

±18.75%

±37.5%

±75%

% of Cycle Time

Example 1, F

NOM

= 25MHz

= 1.25ns

Example 2, F

NOM

= 37.5MHz

= 0.833ns

Example 3, F

NOM

= 50MHz

= 0.625ns

= 1.25ns

Example 4, F

NOM

= 75MHz

= 0.833ns

Example 5, F

NOM

= 100MHz

= 0.625ns

= 1.25ns

Example 6, F

NOM

= 150MHz

= 0.833ns

Example 7, F

NOM

= 200MHz

= 0.625ns

PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE

INDUSTRIAL TEMPERATURE RANGE

IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

DIVIDE SELECTION TABLE

DS [

1:0

]

FB Divide-by-n

Permitted Output Divide-by-n connected to FB

(1)

1 or 2

1, 2, or 4

1 or 2

M M

1, 2, or 4

M H

1 or 2

H M

H H

NOTE:
1. Permissible output division ratios connected to FB. The frequency of the REF input will be F

NOM

/N when the part is configured for frequency multiplication by using an undivided

output for FB and setting DS[

1:0

] to N (N = 1-6, 8, 10, 12).

CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS

nF1:0

Skew (Pair #1, #2)

Skew (Pair #3)

Skew (Pair #4)

(1)

Divide by 2

M M

Zero Skew

M H

H M

H H

Divide by 4

Inverted

(2)

NOTES:
1. LL disables outputs if TEST = MID and

sOE = HIGH.

2. When pair #4 is set to HH (inverted),

sOE disables pair #4 HIGH when PE = HIGH, sOE disables pair #4 LOW when PE = LOW.

RECOMMENDED OPERATING RANGE

Symbol

Description

Min.

Typ.

Max.

Unit

DDQ

Power Supply Voltage

3.3

3.6

Ambient Operating Temperature

-40

+25

+85

° C

INDUSTRIAL TEMPERATURE RANGE

IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Symbol

Parameter

Conditions

Min.

Max.

Unit

Input HIGH Voltage

Guaranteed Logic HIGH (REF, FB Inputs Only)

Input LOW Voltage

Guaranteed Logic LOW (REF, FB Inputs Only)

0.8

IHH

Input HIGH Voltage

(1)

3-Level Inputs Only

0.6

IMM

Input MID Voltage

(1)

3-Level Inputs Only

0.3

/2+0.3

ILL

Input LOW Voltage

(1)

3-Level Inputs Only

0.6

Input Leakage Current

= V

or GND

µ A

(REF, FB Inputs Only)

= Max.

= V

HIGH Level

+200

3-Level Input DC Current

= V

MID Level

+50

µ A

(TEST, FS, nF

[1:0]

, DS

[1:0]

)

= GND

LOW Level

200

Input Pull-Up Current (PE,

PD)

= Max., V

= GND

µ A

Input Pull-Down Current (

sOE)

= Max., V

= V

+100

µ A

Output HIGH Voltage

= Min., I

2mA (LOCK Output)

2.4

DDQ

= Min., I

12mA (nQ

[1:0]

Outputs)

2.4

Output LOW Voltage

= Min., I

= 2mA (LOCK Output)

0.4

DDQ

= Min., I

= 12mA (nQ

[1:0]

Outputs)

0.4

NOTE:

These inputs are normally wired to V

, GND, or unconnected. Internal termination resistors bias unconnected inputs to V

/2. If these inputs are switched, the function and

timing of the outputs may be glitched, and the PLL may require an additional t

LOCK

time before all datasheet limits are achieved.

POWER SUPPLY CHARACTERISTICS

Symbol

Parameter

Test Conditions

(1)

Typ.

(2)

Max.

Unit

DDQ

Quiescent Power Supply Current

= Max., TEST = MID, REF = LOW,

PE = LOW,

sOE = LOW, PD = HIGH

FS = MID, All outputs unloaded

DDPD

Power Down Current

= Max.,

PD = LOW, SOE = LOW

PE = HIGH, TEST = HIGH, FS = HIGH

[1:0]

= HH, DS

[1:0]

= HH

Power Supply Current per Input HIGH

= 3V, V

= Max.,

PD = LOW, TEST = HIGH

(REF and FB inputs only)

FS = L

190

290

DDD

Dynamic Power Supply Current per Output

FS = M

150

230

A/MHz

FS = H

130

200

FS = L , F

VCO

= 50MHz, C

= 0pF

TOT

Total Power Supply Current

FS = M , F

VCO

= 100MHz, C

= 0pF

FS = H, F

VCO

= 200MHz, C

= 0pF

125

NOTES:
1. Measurements are for divide-by-1 outputs, nF

[1:0]

= MM, and DS

[1:0]

= MM.

2. For nominal voltage and temperature.

INDUSTRIAL TEMPERATURE RANGE

IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

Symbol

Parameter

Min.

Typ.

Max.

Unit

NOM

VCO Frequency Range

See Programmable Skew Range and Resolution Table

RPWH

REF Pulse Width HIGH

(1)

RPWL

REF Pulse Width LOW

(1)

Programmable Skew Time Unit

See Control Summary Table

SKEWPR

Zero Output Matched-Pair Skew (xQ

, xQ

)

(2,3)

185

SKEW0

Zero Output Skew (All Outputs)

(4)

0.1

0.25

SKEW1

Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)

(5)

0.1

0.25

SKEW2

Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)

(5)

0.2

0.5

SKEW3

Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)

(5)

0.15

0.5

SKEW4

Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)

(2)

0.3

0.9

DEV

Device-to-Device Skew

(2,6)

0.75

(

)1-3

Static Phase Offset (FS = L, M, H) (FB Divide-by-n = 1, 2, 3)

(7)

0.25

(

Static Phase Offset (FS = H)

(7)

0.25

(

Static Phase Offset (FS = M)

(7)

0.5

(

)L1-6

Static Phase Offset (FS = L) (FB Divide-by-n = 1, 2, 3, 4, 5, 6)

(7)

0.7

(

)L8-12

Static Phase Offset (FS = L) (FB Divide-by-n = 8, 10, 12)

(7)

ODCV

Output Duty Cycle Variation from 50%

PWH

Output HIGH Time Deviation from 50%

(8)

1.5

PWL

Output LOW Time Deviation from 50%

(9)

ORISE

Output Rise Time

0.15

0.7

1.5

OFALL

Output Fall Time

0.15

0.7

1.5

LOCK

PLL Lock Time

(10,11)

0.5

CCJH

Cycle-to-Cycle Output Jitter (peak-to-peak)

100

(divide by 1 output frequency, FS = H, FB divide-by-n=1,2)

CCJHA

Cycle-to-Cycle Output Jitter (peak-to-peak)

150

(divide by 1 output frequency, FS = H, FB divide-by-n=any)

CCJM

Cycle-to-Cycle Output Jitter (peak-to-peak)

150

(divide by 1 output frequency, FS = M)

CCJL

Cycle-to-Cycle Output Jitter (peak-to-peak)

200

(divide by 1 output frequency, FS = L, F

REF

> 3MHz)

CCJLA

Cycle-to-Cycle Output Jitter (peak-to-peak)

300

(divide by 1 output frequency, FS = L, F

REF

< 3MHz)

NOTES:
1.

Refer to Input Timing Requirements table for more detail.

Skew is the time between the earliest and the latest output transition among all outputs for which the same t

delay has been selected when all are loaded with the specified

load.

SKEWPR

is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t

SK(0)

is the skew between outputs when they are selected for 0t

There are 3 classes of outputs: Nominal (multiple of t

delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-

by-4 mode). Test condition: nF0:1=MM is set on unused outputs.

DEV

is the output-to-output skew between any two devices operating under the same conditions (V

DDQ

, V

, ambient temperature, air flow, etc.)

is measured with REF input rise and fall times (from 0.8V to 2V) of 0.5ns. Measured from 1.5V on REF to 1.5V on FB.

Measured at 2V.

Measured at 0.8V.

10. t

LOCK

is the time that is required before synchronization is achieved. This specification is valid only after V

DDQ

is stable and within normal operating limits. This parameter

is measured from the application of a new signal or frequency at REF or FB until t

is within specified limits.

11. Lock detector may be unreliable for input frequencies less than approximately 4MHz, or for input signals which contain significant jitter.

INDUSTRIAL TEMPERATURE RANGE

IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

RE F

OTH ER Q

INV ER TE D Q

REF D IVIDE D B Y 2

REF D IVIDE D B Y 4

R EF

S KEW 2

SK EW 3, 4

SK EW 1, 3, 4

SK EW 2, 4

SK EW 3, 4

SKEW 3, 4

S KEW 2

S KEW P R

SK EW 0, 1

CCJH, HA,

M, L, LA

O DC V

RP W H

R PW L

S KEW P R

SKEW 0, 1

(

)

AC TIMING DIAGRAM

NOTES:
PE:

The AC Timing Diagram applies to PE=V

. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge

of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.

Skew:

The time between the earliest and the latest output transition among all outputs for which the same t

delay has been selected when all are loaded with 20pF and terminated

with 75

to V

DDQ

/2.

SKEWPR

The skew between a pair of outputs (xQ

and xQ

) when all eight outputs are selected for 0t

SKEW0

The skew between outputs when they are selected for 0t

DEV

The output-to-output skew between any two devices operating under the same conditions (V

DDQ

, ambient temperature, air flow, etc.)

ODCV

The deviation of the output from a 50% duty cycle. Output pulse width variations are included in t

SKEW2

and t

SKEW4

specifications.

PWH

is measured at 2V.

PWL

is measured at 0.8V.

ORISE

and t

OFALL

are measured between 0.8V and 2V.

LOCK

The time that is required before synchronization is achieved. This specification is valid only after V

DDQ

is stable and within normal operating limits. This parameter

is measured from the application of a new signal or frequency at REF or FB until t

is within specified limits.

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